Patents by Inventor Hung-Wei Chang

Hung-Wei Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11031279
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having reduced trench loading effect. The present disclosure provides a novel multi-layer cap film incorporating one or more oxygen-based layers for reducing trench loading effects in semiconductor devices. The multi-layer cap film can be made of a metal hard mask layer and one or more oxygen-based layers. The metal hard mask layer can be formed of titanium nitride (TiN). The oxygen-based layer can be formed of tetraethyl orthosilicate (TEOS).
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Kai Sun, Yi-Wei Chiu, Hung Jui Chang, Chia-Ching Tsai
  • Patent number: 11031291
    Abstract: A semiconductor structure includes a substrate including a first region and a second region, a first channel layer disposed in the first region and a second channel layer disposed in the second region, a first dielectric layer disposed on the first channel layer and a second dielectric layer disposed on the second channel layer, and a first gate electrode disposed on the first dielectric layer and a second gate electrode disposed on the second dielectric layer. The first channel layer in the first region includes Ge compound of a first Ge concentration, the second channel layer in the second region includes Ge compound of a second Ge concentration. The first Ge concentration in the first channel layer is greater than the second Ge concentration in the second channel layer.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: I-Ming Chang, Chung-Liang Cheng, Hsiang-Pi Chang, Hung-Chang Sun, Yao-Sheng Huang, Yu-Wei Lu, Fang-Wei Lee, Ziwei Fang, Huang-Lin Chao
  • Patent number: 11022707
    Abstract: A method of determining an earthquake event for an earthquake detecting system includes retrieving at least one initial wave characteristic related to each earthquake data among a plurality of earthquake data; utilizing a support vector classification (SVC) method to establish an earthquake determination model according to the initial wave characteristic; and determining whether new earthquake data belong to an earthquake event or a non-earthquake event according to the earthquake determination model when the new earthquake data are received.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: June 1, 2021
    Assignee: National Applied Research Laboratories
    Inventors: Ting-Yu Hsu, Rih-Teng Wu, Shyu-Yu Wu, Pei-Yang Lin, Shieh-Kung Huang, Hung-Wei Chiang, Kung-Chun Lu, Kuo-Chun Chang
  • Publication number: 20210150950
    Abstract: Electronic devices and methods for compensating for aging or other effects in a display during a non-transmitting state (off state) of the display. Sensing may include emissive element sensing of the display and/or thin film transistor sensing of the display. Compensating for the effects may preserve or increase a uniformity of transmission of the display.
    Type: Application
    Filed: August 31, 2018
    Publication date: May 20, 2021
    Inventors: Chin-Wei Lin, Hung Sheng Lin, Hyunsoo Kim, Hyunwoo Nho, Injae Hwang, Jesse A. Richmond, Jie Won Ryu, Junhua Tan, Kavinaath Murugan, Kingsuk Brahma, Shengkui Gao, Shiping Shen, Sun-Il Chang, Myung-Je Cho, Yafei Bi
  • Publication number: 20210141407
    Abstract: The present invention discloses an AVS scanning method, wherein the AVS scanning method includes the steps of: mounting a system on chip (SoC) on a printed circuit board (PCB), and connecting the SoC to a storage unit; enabling the SoC to read a boot code from the storage unit, and executing the boot code to perform an AVS scanning operation on the SoC to determine a plurality of target supply voltages respectively corresponding to a plurality of operating frequencies of the SoC to establish an AVS look-up table; and storing the AVS look-up table into the SoC or the storage unit.
    Type: Application
    Filed: November 3, 2020
    Publication date: May 13, 2021
    Inventors: Chao-Min Lai, Hung-Wei Wang, Tang-Hung Chang, Han-Chieh Hsieh, Chun-Yi Kuo
  • Patent number: 11004730
    Abstract: An interconnect structure and a method of forming are provided. The method includes forming an opening in a dielectric layer and an etch stop layer, wherein the opening extends only partially through the etch stop layer. The method also includes creating a vacuum environment around the device. After creating the vacuum environment around the device, the method includes etching through the etch stop layer to extend the opening and expose a first conductive feature. The method also includes forming a second conductive feature in the opening.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ching Tsai, Yi-Wei Chiu, Hung Jui Chang, Li-Te Hsu
  • Publication number: 20210134749
    Abstract: In an embodiment, a device includes: a semiconductor substrate; a contact pad on the semiconductor substrate; a passivation layer on the contact pad and the semiconductor substrate; a die connector extending through the passivation layer, the die connector being physically and electrically coupled to the contact pad, the die connector including a first conductive material, the first conductive material being a Lewis acid having a first acid hardness/softness index; a dielectric layer on the die connector and the passivation layer; and a protective layer disposed between the dielectric layer and the die connector, the protective layer surrounding the die connector, the protective layer including a coordination complex of the first conductive material and an azole, the azole being a Lewis base having a first ligand hardness/softness index, where a product of the first acid hardness/softness index and the first ligand hardness/softness index is positive.
    Type: Application
    Filed: October 31, 2019
    Publication date: May 6, 2021
    Inventors: Hung-Jui Kuo, Chia-Wei Wang, Hui-Jung Tsai, Yu-Tzu Chang
  • Patent number: 10997917
    Abstract: A display may have an array of pixels each of which has a light-emitting diode such as an organic light-emitting diode. A drive transistor and an emission transistor may be coupled in series with the light-emitting diode of each pixel between a positive power supply and a ground power supply. The pixels may include first and second switching transistors. A data storage capacitor may be coupled between a gate and source of the drive transistor in each pixel. Signal lines may be provided in columns of pixels to route signals such as data signals, sensed drive currents from the drive transistors, and predetermined voltages between display driver circuitry and the pixels. The switching transistors, emission transistors, and drive transistors may include semiconducting-oxide transistors and silicon transistors and may be n-channel transistors or p-channel transistors.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: May 4, 2021
    Assignee: Apple Inc.
    Inventors: Chin-Wei Lin, Hung Sheng Lin, Shih Chang Chang, Shinya Ono
  • Patent number: 10998259
    Abstract: A dielectric layer is formed over a substrate, an anti-reflective layer is formed over the dielectric layer, and a first hardmask is formed over the anti-reflective layer. A via opening and a trench opening are formed within the dielectric layer using the anti-reflective layer and the first hardmask as masking materials. After the formation of the trench opening and the via opening, the first hardmask is removed. An interconnect is formed within the openings, and the interconnect has a via with a profile angle of between about 70° and about 80° and a depth ratio of between about 65% and about 70%.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ching Tsai, Yi-Wei Chiu, Hung Jui Chang, Li-Te Hsu
  • Publication number: 20210117187
    Abstract: A computing in memory method for a memory device is provided. The computing in memory method includes: based on a stride parameter, unfolding a kernel into a plurality of sub-kernels and a plurality of complement sub-kernels; based on the sub-kernels and the complement sub-kernels, writing a plurality of weights into a plurality of target memory cells of a memory array of the memory device; inputting an input data into a selected word line of the memory array; performing a stride operation in the memory array; temporarily storing a plurality of partial sums; and summing the stored partial sums into a stride operation result when all operation cycles are completed.
    Type: Application
    Filed: September 21, 2020
    Publication date: April 22, 2021
    Inventors: Hung-Sheng CHANG, Han-Wen HU, Yueh-Han WU, Tse-Yuan WANG, Yuan-Hao CHANG, Tei-Wei KUO
  • Publication number: 20210118994
    Abstract: A device includes a fin extending from a semiconductor substrate, a gate stack over and along a sidewall of the fin, an isolation region surrounding the gate stack, an epitaxial source/drain region in the fin and adjacent the gate stack, and a source/drain contact extending through the isolation region, including a first silicide region in the epitaxial source/drain region, the first silicide region including NiSi2, a second silicide region on the first silicide region, the second silicide region including TiSix, and a conductive material on the second silicide region.
    Type: Application
    Filed: October 18, 2019
    Publication date: April 22, 2021
    Inventors: Yan-Ming Tsai, Chih-Wei Chang, Ming-Hsing Tsai, Sheng-Hsuan Lin, Hung-Hsu Chen, Wei-Yip Loh
  • Publication number: 20190159570
    Abstract: The present invention provides a steam-off gel nail removal device comprising a casing. A plurality of finger insertion holes for finger insertion is disposed on one side of the casing, and a receiving space is disposed on the inner side of the casing. The receiving space has therein a heating device and a control device connected to the heating device. A gel polish removing solution container is disposed on the inner side of the receiving space. The heating device is disposed on one side of the gel polish removing solution container to heat the gel polish removing solution container. The steam-off gel nail removal device of the present invention further comprises a safety switch and a finger separation unit for taking safety-enhancing measures to ensure user safety. The finger insertion holes are sufficient for every user's left hand or right hand to be placed comfortably on the steam-off gel nail removal device.
    Type: Application
    Filed: January 2, 2018
    Publication date: May 30, 2019
    Inventors: Wan Chieh HSIEH, Pai Yao HSIEH, Hung Wei CHANG, Kuan Chen LIAO
  • Patent number: 9497865
    Abstract: A method for forming a printed circuit board includes providing a substrate including a first device region, a second device region and a dicing channel region between the first device region and the second device region. A first circuit is formed on the substrate. An insulating layer is formed on the first circuit and the substrate. At least one build-up circuit is formed on the insulating layer. A photoresist layer is formed on the at least one build-up circuit. An image transferring process is performed to pattern the photoresist layer to form a dam structure in the dicing channel region. A solder mask layer is formed on the at least one build-up circuit. The dam structure is removed to form a trench in the solder mask layer.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: November 15, 2016
    Assignee: Nan Ya PCB Corp.
    Inventors: Hung-Wei Chang, Tai-Yi Chou
  • Publication number: 20140216787
    Abstract: A method for forming a printed circuit board is disclosed. A substrate including a first device region, a second device region and a dicing channel region between the first device region and the second device region is provided. A first circuit is formed on the substrate. An insulating layer is formed on the first circuit and the substrate. At least one build-up circuit is formed on the insulating layer. A photoresist layer is formed on the at least one build-up circuit. An image transferring process is performed to pattern the photoresist layer to form a dam structure in the dicing channel region. A solder mask layer is formed on the at least one build-up circuit. The dam structure is removed to form a trench in the solder mask layer.
    Type: Application
    Filed: October 1, 2013
    Publication date: August 7, 2014
    Inventors: Hung-Wei Chang, Tai-Yi Chou
  • Publication number: 20140055943
    Abstract: A metal shock absorber, an assembly of a metal shock absorber and a media recording unit, and a media recording device are provided. The metal shock absorber has a pair of horizontal portions, a perpendicular portion connected between the horizontal portions, and a pair of limiting portions. Each of the horizontal portions has a first arcuate protrusion protruding towards another first arcuate protrusion. The perpendicular portion is perpendicularly connected between the pair of horizontal portions, and has an assembling arm. The limiting portions are disposed at opposite sides of the perpendicular portion that are not connected with the horizontal portions. Since the thickness, the tolerance and costs of the metal shock absorber are less than those of the conventional rubber shock absorber, the assembly of the metal shock absorber with the media recording unit has a favorable assembly reliability, and therefore costs of the recording device are effectively lowered.
    Type: Application
    Filed: March 15, 2013
    Publication date: February 27, 2014
    Applicants: Kinpo Electronics, Inc., Cal-Comp Electronics & Communications Company Limited
    Inventors: Hung-Wei Chang, Yih-Her Lin
  • Patent number: 8148833
    Abstract: An on-road energy conversion and vibration absorber apparatus receives the kinetic energy from moving vehicles and pedestrians when being weighed down, and converts the received kinetic energy into a potential energy using a restorable elastic element compressing a fluid thereby storing the potential energy in a pressure chamber, and then conducting the pressurized fluid to pass though a check valve along a conduit and drive a vane wheel by releasing its potential energy. The vane wheel in turn drives a generator to generate electric energy, and the vibration of the vehicles is alleviated by cushion effect provided by the apparatus.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: April 3, 2012
    Inventors: Hung-Wei Chang, Chih-Yang Lee
  • Publication number: 20110215593
    Abstract: An on-road energy conversion and vibration absorber apparatus receives the kinetic energy from moving vehicles and pedestrians when being weighed down, and converts the received kinetic energy into a potential energy using a restorable elastic element compressing a fluid thereby storing the potential energy in a pressure chamber, and then conducting the pressurized fluid to pass though a check valve along a conduit and drive a vane wheel by releasing its potential energy. The vane wheel in turn drives a generator to generate electric energy, and the vibration of the vehicles is alleviated by cushion effect provided by the apparatus.
    Type: Application
    Filed: May 18, 2011
    Publication date: September 8, 2011
    Inventors: Hung-Wei Chang, Chih-Yang Lee
  • Patent number: D857993
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: August 27, 2019
    Assignee: COSMEX CO., LTD.
    Inventors: Wan Chieh Hsieh, Pai Yao Hsieh, Hung Wei Chang, Kuan Chen Liao
  • Patent number: D858882
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: September 3, 2019
    Assignee: COSMEX CO., LTD.
    Inventors: Wan Chieh Hsieh, Pai Yao Hsieh, Hung Wei Chang, Kuan Chen Liao
  • Patent number: D890431
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: July 14, 2020
    Assignee: COSMEX CO. LTD.
    Inventors: Wan Chieh Hsieh, Pai Yao Hsieh, Hung Wei Chang, Hao-Hong Ciou