Abstract: A thin film transistor, a semiconductor device having a thin film transistor and a method of fabricating a thin film transistor are provided. The thin film transistor includes a gate metal; a gate dielectric layer disposed on the gate metal; a semiconductor layer disposed on the gate dielectric layer; an interlayer dielectric disposed on the semiconductor layer and having a contact hole over the semiconductor layer; a source/drain metal disposed in the contact hole; a first liner disposed between the interlayer dielectric and the source/drain metal; and a second liner disposed between the first liner and the source/drain metal and being in contact with the semiconductor layer in the contact hole.

Abstract: Embodiments of the present disclosure provide a side-channel dynamic random access memory (DRAM) cell and cell array that utilizes a vertical design with side channel transistors. A dielectric layer disposed over a substrate. A gate electrode is embedded in the dielectric layer. A channel layer wraps the gate electrode and a conductive structure is adjacent to the channel layer, with the channel layer interposed between the gate electrode and the conductive structure. The semiconductor structure also includes a dielectric structure disposed over the conductive structure and the gate electrode, the channel layer extending up through the dielectric structure.

Abstract: A transistor includes a gate, a channel layer, a gate insulation layer, a passivation layer, a liner, a first signal line, and a second signal line. The first signal line is embedded in the passivation layer to form a first via in the passivation layer and overlapping the channel layer. The second signal line is embedded in the passivation layer to form a second via in the passivation layer overlapping the channel layer. The second signal line is in contact with the channel layer. The liner includes an insulation region and a conductive region connected with the insulation region. The insulation region is disposed over the passivation layer and on sidewalls of the first via. The conductive region is disposed under a bottom of the first via and connected with the channel layer. The first signal line is electrically connected with the channel layer through the conductive region.

Abstract: A transistor includes a gate, a channel layer, a gate insulation layer, a passivation layer, a liner, a first signal line, and a second signal line. The first signal line is embedded in the passivation layer to form a first via in the passivation layer and overlapping the channel layer. The second signal line is embedded in the passivation layer to form a second via in the passivation layer overlapping the channel layer. The second signal line is in contact with the channel layer. The liner includes an insulation region and a conductive region connected with the insulation region. The insulation region is disposed over the passivation layer and on sidewalls of the first via. The conductive region is disposed under a bottom of the first via and connected with the channel layer. The first signal line is electrically connected with the channel layer through the conductive region.

Abstract: A thin film transistor includes an insulating matrix layer including an opening therein, a hydrogen-blocking dielectric barrier layer continuously extending over a bottom surface and sidewalls of the opening and over a top surface of the insulating matrix layer, a gate electrode located within the opening, a stack of a gate dielectric and a semiconducting metal oxide plate overlying the gate electrode and horizontally-extending portions of the hydrogen-blocking dielectric barrier layer that overlie the insulating matrix layer, and a source electrode and a drain electrode contacting a respective portion of a top surface of the semiconducting metal oxide plate.

Abstract: The present disclosure relates a ferroelectric field-effect transistor (FeFET) device. The FeFET device includes a ferroelectric structure having a first side and a second side. A gate structure is disposed along the first side of the ferroelectric structure, and an oxide semiconductor is disposed along the second side of the ferroelectric structure. The oxide semiconductor has a first semiconductor type. A source region and a drain region are disposed on the oxide semiconductor. The gate structure is laterally between the source region and the drain region. A polarization enhancement structure is arranged on the oxide semiconductor between the source region and the drain region. The polarization enhancement structure includes a semiconductor material or an oxide semiconductor material having a second semiconductor type that is different than the first semiconductor type.

Abstract: An active device substrate includes a substrate, a silicon layer, a first insulating layer, a first gate, a first dielectric layer, a first transfer electrode, a second transfer electrode, and a second dielectric layer. Two openings penetrate through the first dielectric layer and overlap the silicon layer. The first transfer electrode and the second transfer electrode are respectively located in the two openings. The second dielectric layer is located on the first transfer electrode and the second transfer electrode. Two first through-holes penetrate through the second dielectric layer. The first transfer electrode and the second transfer electrode are etch stop layers of the two first through-holes.

Abstract: A transistor and method of making the same, the method including: forming a seed layer on a first dielectric layer, the seed layer including a crystalline metal oxide semiconductor material; depositing an amorphous silicon layer on the seed layer; annealing the amorphous silicon layer to form a single-crystal silicon (c-Si) layer; patterning the seed layer and the c-Si layer to form a hybrid channel layer; forming a gate dielectric layer on the hybrid channel layer; forming a gate electrode on the gate dielectric layer; and forming source and drain electrodes that respectively electrically contact a source region and a drain region of the hybrid channel layer.

Abstract: Field effect transistors and method of making. The field effect transistors include a pair of active regions in a channel layer, a channel region located between the pair of active regions and a self-aligned passivation layer located on a surface of the pair of active regions.

Abstract: A transistor device and method of making the same, the transistor device including: a substrate; a word line disposed on the substrate; a gate insulating layer disposed on the word line; a dual-layer semiconductor channel including: a first channel layer disposed on the gate insulating layer; and a second channel layer disposed on the first channel layer, such that the second channel layer contacts side and top surfaces of the first channel layer; and source and drain electrodes electrically coupled to the second channel layer. When a voltage is applied to the word line, the first channel layer has a first electrical resistance and the second channel layer has a second electrical resistance that is different from the first electrical resistance.

Abstract: A transistor includes a gate, a channel layer, a gate insulation layer, a passivation layer, a liner, a first signal line, and a second signal line. The first signal line is embedded in the passivation layer to form a first via in the passivation layer and overlapping the channel layer. The second signal line is embedded in the passivation layer to form a second via in the passivation layer overlapping the channel layer. The second signal line is in contact with the channel layer. The liner includes an insulation region and a conductive region connected with the insulation region. The insulation region is disposed over the passivation layer and on sidewalls of the first via. The conductive region is disposed under a bottom of the first via and connected with the channel layer. The first signal line is electrically connected with the channel layer through the conductive region.

Abstract: A thin film transistor and method of making the same, the thin film transistor including: a substrate; a word line disposed on the substrate; a semiconductor layer disposed on the substrate, the semiconductor layer having a source region, a drain region, and a channel region disposed between the source and drain regions and overlapping with the word line in a vertical direction perpendicular to a plane of the substrate; a hydrogen diffusion barrier layer overlapping with the channel region in the vertical direction; a gate dielectric layer disposed between the channel region and the word line; and source and drain electrodes respectively electrically coupled to the source and drain regions.

Abstract: An active device substrate includes a substrate, a silicon layer, a first insulating layer, a first gate, a first dielectric layer, a first transfer electrode, a second transfer electrode, and a second dielectric layer. Two openings penetrate through the first dielectric layer and overlap the silicon layer. The first transfer electrode and the second transfer electrode are respectively located in the two openings. The second dielectric layer is located on the first transfer electrode and the second transfer electrode. Two first through-holes penetrate through the second dielectric layer. The first transfer electrode and the second transfer electrode are etch stop layers of the two first through-holes.

Abstract: A pixel structure includes a metal oxide semiconductor layer, a first insulating layer, a second insulating layer, a first conductive layer, a passivation layer, a second conductive layer and a pixel electrode. The metal oxide semiconductor layer includes a second semiconductor pattern. The first insulating layer includes a first capacitance dielectric pattern disposed on the second semiconductor pattern. The second insulating layer includes a second capacitance dielectric pattern disposed on the first capacitance dielectric pattern. The first conductive layer includes a electrode pattern disposed on the second capacitance dielectric pattern. The passivation layer covers the first conductive layer. The second conductive layer includes a second electrode disposed on the passivation layer. The second electrode is electrically connected to the second semiconductor pattern. The second electrode is disposed to overlap the electrode pattern.

Abstract: A pixel structure includes a metal oxide semiconductor layer, a first insulating layer, a second insulating layer, a first conductive layer, a passivation layer, a second conductive layer and a pixel electrode. The metal oxide semiconductor layer includes a second semiconductor pattern. The first insulating layer includes a first capacitance dielectric pattern disposed on the second semiconductor pattern. The second insulating layer includes a second capacitance dielectric pattern disposed on the first capacitance dielectric pattern. The first conductive layer includes a electrode pattern disposed on the second capacitance dielectric pattern. The passivation layer covers the first conductive layer. The second conductive layer includes a second electrode disposed on the passivation layer. The second electrode is electrically connected to the second semiconductor pattern. The second electrode is disposed to overlap the electrode pattern.

Abstract: The present invention relates to an erasing method for nonvolatile memory, which uses forward bias between the source/drain region and body contact to inject majority carriers into the body, and then accelerates the majority carriers by an electric field between the body and the gate to energize the majority carriers to overcome the oxide barrier and to erase the nonvolatile memory.

Abstract: The present invention relates to an erasing method for nonvolatile memory, which uses forward bias between the source/drain region and body contact to inject majority carriers into the body, and then accelerates the majority carriers by an electric field between the body and the gate to energize the majority carriers to overcome the oxide barrier and to erase the nonvolatile memory.

Abstract: A pixel driving circuit of this invention utilizes a storage capacitor and an active loading circuit to serve as a pixel data storage buffer for each pixel. The pixel driving circuit of this invention can write the whole-panel pixel data for a next frame in these storage buffers during the illuminating time of a backlight. When changing the frames, the whole-panel pixels synchronously read the pixel data pre-stored in these storage buffers. As a result, the write-in time of the whole-panel pixel data is reduced and the illuminating time of the backlight is relatively increased.

Abstract: A method for manufacturing copper wires on a substrate for a flat panel display device is disclosed. The method comprises following steps: providing a substrate; forming a seed layer on the surface; forming a patterned photoresist on the surface of the seed layer to expose a part of the seed layer; and plating a copper layer on the exposed part of the seed layer. As the copper layer is plated, an electrolyte solution comprises a sulfur-containing compound is used. The angle between the surface of the copper layer and the contact surface of the seed layer is greater than 0 degree and less than 90 degree. Through the method illustrated above, the film step-coverage in the following process can be improved, the generated voids in device can be reduced, the manufacturing steps can be simplified, and the complicated etching process can be avoided.

Abstract: A method for manufacturing copper wires on a substrate for a flat panel display device is disclosed. The method comprises following steps: providing a substrate; forming a seed layer on the surface; forming a patterned photoresist on the surface of the seed layer to expose a part of the seed layer; and plating a copper layer on the exposed part of the seed layer. As the copper layer is plated, an electrolyte solution comprises a sulfur-containing compound is used. The angle between the surface of the copper layer and the contact surface of the seed layer is greater than 0 degree and less than 90 degree. Through the method illustrated above, the film step-coverage in the following process can be improved, the generated voids in device can be reduced, the manufacturing steps can be simplified, and the complicated etching process can be avoided.