Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.

Abstract: A light-source module includes an optical film and at least one light-source unit, which together enclose a space. The light-source unit includes a reflective assembly, a light-concentrating unit and at least one light-emitting assembly. The light-concentrating unit has a light exiting end and a light incidence end, and the light exiting end faces the space enclosed by the light-source unit and the optical film. The optical-axis direction of the light-emitting assembly is defined as a first direction, and the direction perpendicular to both the first direction and the optical film is defined as a second direction. The length of the light-concentrating unit in the first direction is defined as a light-concentrating distance, the width of the light exiting end in the second direction is defined as a light exiting width, and the ratio of the light-concentrating distance over the light exiting width is greater than 0.5 but less than 10.

Abstract: A light emitting unit includes a light source device and a reflector. The light source device extends in parallel with an extension direction, and is capable of providing a light beam. The reflector is configured under the light source device and extends in parallel with the extension direction. The reflector has a first protrusion and a pair of second protrusions located on two sides of the first protrusion, the first protrusion has a peak portion and two trough portions, the second protrusion has a peak portion and a trough portion, and the two trough portions of the first protrusion are respectively connected to the trough portions of the two second protrusions to provide a fluctuant reflection surface, and a height of a cross section contour of the pair of the second protrusions in parallel with the extension direction is decreased from a centre to two ends of the reflector.

Abstract: Methods of forming a semiconductor device are provided. The methods include, for example, forming a low-k dielectric having a continuous planar surface, and, after forming the low-k dielectric, subjecting the continuous planar surface of the low-k dielectric to an ethylene plasma enhanced chemical vapor deposition (PECVD) treatment.

Abstract: A bulk heterojunction solar cell comprises an electron donor, an electron acceptor, and a multi-substituted fullerene derivative. The electron acceptor further comprises a nano-scale electron acceptor material, and a meso-scale mixture of electron donor/acceptor material. The multi-substituted fullerene derivative further comprises a single fullerene structure and a multi-substituted derivative connected to the single fullerene structure. The multi-substituted fullerene derivative is utilized to prevent the meso-scale mixture of electron donor/acceptor material from large-scale segregation of acceptor over a specific temperature after a specific period (thermally unstable state), thereby maintaining the thermal stability and the sizes of the nano-scale acceptor material and meso-scale mixture of electron donor/acceptor material. In the conventional knowledge, the large-scale segregation and corresponding degradation of power efficiency are cause mainly by the nano-scale acceptor material.

Abstract: A light source module is provided, which includes at least one light emitting unit and at least one light guide element. The light emitting unit includes a light source and a lens structure. The light source is used for emitting a light beam. The lens structure has a bottom surface, a top surface opposite to the bottom surface, and a first surface connecting the bottom surface and the top surface. The bottom surface has a first recess and a second recess connecting the first recess and the first surface. The top surface has a third recess. The light guide element includes at least one opening and a plurality of first optical micro-structures disposed beside the opening. The light emitting unit is disposed in the opening. The light beam passes through the lens structure and enters the light guide element via the opening.

Abstract: A backlight module including a chamber, a bottom reflector, a plurality of light sources, and a plurality of lenses is provided. The chamber has a bottom surface and a side surface. The bottom reflector is disposed inside the chamber and located on the bottom surface. The light sources are disposed inside the chamber and located above the bottom reflector. Each light source is adjacent to the side surface and provides light. The lenses are disposed on a transmission path of the light. Each lens has a back surface, a cavity on the back surface, and a light-emitting surface. The cavity has a light-incident surface. Each light source is arranged corresponding to one of the lenses and adjacent to the cavity. The light, after passing the lenses, is divided into light beams with different propagating directions. The light beams irradiate the bottom reflector.

Abstract: The present invention is directed to forming memory wordlines having a relatively lower sheet resistance. In one embodiment, a control-gate poly layer including a first and a second poly-Si portion is deposited. a The first poly-Si portion is deposited on a semiconductor substrate using a first precursor gas flow rate. A The second poly-Si portion is deposited on the first poly-Si portion using a second precursor gas flow rate, where the second precursor flow rate higher than the first precursor gas flow rate. A tungsten silicide layer is then deposited. A wordline is formed from a stacked film of the control-gate poly layer and tungsten silicide layer. The control-gate poly layer and tungsten silicide layer are then patterned to form a gate electrode, and a implantation process is made, after or before, forming the tungsten silicide layer.

Abstract: The present invention is directed to forming memory wordlines having a relatively lower sheet resistance. In one embodiment, a first poly-Si portion is deposited on a semiconductor substrate using a first precursor gas flow rate. A second poly-Si portion is deposited using a second precursor gas flow rate, where the second precursor flow rate higher than the first precursor gas flow rate. A tungsten silicide layer is deposited using silane gas. Wordlines are formed in trenches from poly-Si and WSix. A gate electrode is implanted.

Abstract: A method of forming a suicide layer is described. A silicon layer is provided. Ions are introduced in the silicon layer. A metal layer is formed on the silicon layer. An annealing process is performed so that the silicon layer reacts with the metal layer to form the metal silicide layer. Thereafter, the unreacted metal layer is removed. The uniformity of the grain size and the grain distribution of the metal silicide layer are improved by introducing the ions in the silicon layer before performing the annealing process, so that sheet resistance of the metal silicide layer is reduced.

Abstract: The present invention proposes an application of controlling gas valves to reduce particles from the CVD process. First, the actions of opening and closing a gas valve are added to let particles possibly adhering on the gas valve fall during the idle period between the CVD processes of a wafer and the next wafer. Next, an inert gas is led in to purge the gas valve and the reaction chamber. Finally, a gas-extracting means is used to extract the gas out. The actions of opening and closing the gas valve only take a few seconds so that the time of the next wafer entering the reaction chamber to perform the CVD process will not be influenced. The present invention has the advantage of increasing the yield of wafer while the production is not influenced and the original fabrication equipments need not be changed.

Abstract: The present invention proposes an application of controlling gas valves to reduce particles from the CVD process. First, the actions of opening and closing a gas valve are added to let particles possibly adhering on the gas valve fall during the idle period between the CVD processes of a wafer and the next wafer. Next, an inert gas is led in to purge the gas valve and the reaction chamber. Finally, a gas-extracting means is used to extract the gas out. The actions of opening and closing the gas valve only take a few seconds so that the time of the next wafer entering the reaction chamber to perform the CVD process will not be influenced. The present invention has the advantage of increasing the yield of wafer while the production is not influenced and the original fabrication equipments need not be changed.