Abstract: A method of performing power saving control on a display device includes: generating, by a timing controller of the display device, a power saving start indication and a power saving end indication in response to changing of a refresh rate of the display device; receiving, by a source driver of the display device, the power saving start indication and the power saving end indication; in response to the power saving start indication, allowing a part of circuitry of the source driver to be powered down during a vertical blanking interval; and in response to the power saving end indication, allowing the powered down part of circuitry of the source driver to be woken up during the vertical blanking interval.

Abstract: A method of forming a semiconductor package includes the following operations. A first integrated circuit structure is provided, and the first integrated circuit structure includes a first substrate and a silicon layer over the first substrate. A plasma treatment is performed to transform a top portion of the silicon layer to a first bonding layer on the remaining silicon layer of the first integrated circuit structure. A second integrated circuit structure is provided, and the second integrated circuit structure includes a second substrate and a second bonding layer over the second substrate. The second integrated circuit structure is bonded to the first integrated circuit structure through the second bonding layer of the second integrated circuit structure and the first bonding layer of the first integrated circuit structure.

Abstract: A method of performing power saving control on a display device includes: generating, by a timing controller of the display device, a power saving start indication and a power saving end indication in response to changing of a refresh rate of the display device; receiving, by a source driver of the display device, the power saving start indication and the power saving end indication; in response to the power saving start indication, allowing a part of circuitry of the source driver to be powered down during a vertical blanking interval; and in response to the power saving end indication, allowing the powered down part of circuitry of the source driver to be woken up during the vertical blanking interval.

Abstract: Semiconductor structures and formation processes thereof are provided. A semiconductor structure of the present disclosure includes a semiconductor substrate, a plurality of transistors disposed on the semiconductor substrate and comprising a plurality of gate structures extending lengthwise along a first direction, a metallization layer disposed over the plurality of transistors, the metallization layer comprising a plurality of metal layers and a plurality of contact vias, a dielectric layer over the metallization layer, a plurality of dielectric fins extending parallel along the first direction and disposed over the dielectric layer, a semiconductor layer disposed conformally over the plurality of dielectric fins, a source contact and a drain contact disposed directly on the semiconductor layer, and a gate structure disposed over the semiconductor layer and between the source contact and the drain contact.

Abstract: A system and method for providing and programming a programmable inductor is provided. The structure of the programmable inductor includes multiple turns, with programmable interconnects incorporated at various points around the turns to provide a desired isolation of the turns during programming. In an embodiment the programming may be controlled using the size of the vias, the number of vias, or the shapes of the interconnects.

Abstract: A display panel includes a substrate and a plurality of pixel structures disposed on the substrate. Each of the pixel structures includes a first light-emitting element, a second light-emitting element, and a third light-emitting element. The first light-emitting element is disposed on the substrate and configured to generate a first colored light. A light output surface of the first light-emitting element includes a combined region. The second light-emitting element is disposed on a part of the combined region and configured to generate a second colored light. The third light-emitting element is disposed on the other part of the combined region and configured to generate a third colored light.

Abstract: Disclosed herein are novel single-stranded anti-sense oligonucleotides (ASOs) capable of reducing the transcription of thioredoxin domain containing protein 5 (TXNDC5) mRNA. Also disclosed is use of the single-stranded ASOs as disclosed herein for manufacturing medicaments suitable for treating a disease associated with upregulation of TXNDC5. Accordingly, a pharmaceutical composition comprising the disclosed ASO molecules is provided; as well as a method of treating a subject suffering from TXNDC5-mediated disease via administering to the subject the disclosed single-stranded ASO molecules.

Abstract: A device includes a fin extending from a semiconductor substrate, a gate stack over and along a sidewall of the fin, an isolation region surrounding the gate stack, an epitaxial source/drain region in the fin and adjacent the gate stack, and a source/drain contact extending through the isolation region, including a first silicide region in the epitaxial source/drain region, the first silicide region including NiSi2, a second silicide region on the first silicide region, the second silicide region including TiSix, and a conductive material on the second silicide region.

Abstract: Image dewarping includes capturing a source image from a camera, selecting an input row of pixels from the source image, if the input row of pixels comprises a plurality of input pixels in a region of interest in the source image, storing the plurality of input pixels to a memory to generate an input segment of pixels, when a plurality of pixels required to generate an output row of pixels are all stored in the memory, reading from the memory the plurality of pixels corresponding to the output row of pixels, and performing coordinate transformation on the plurality of pixels to generate the output row of pixels, and when coordinate transformation has been completed on the plurality of pixels, releasing from the memory an input segment of pixels of the plurality of input segments of pixels that does not correspond to other output rows of pixels.

Abstract: A package structure includes an integrated circuit die and an encapsulant laterally encapsulating the integrated circuit die. The integrated circuit die includes a semiconductor substrate, an interconnection structure, a testing pad, a dummy post, a conductive post, and a protection layer. The interconnection structure is disposed on the semiconductor substrate. The testing pad is disposed on the interconnection structure. The dummy post is disposed on the testing pad. The conductive post is aside the dummy post. The protection layer is disposed between the conductive post and the dummy post.

Abstract: An electronic device comprises a display and a controller. The controller is configured to provide a first frequency refresh rate to the display. The controller is also configured to generate a control signal configured to control emission of a light emitting diode of a display pixel of the display at a second frequency based on whether the first frequency refresh rate of the display is less than a predetermined threshold value.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a first semiconductor module, a reorientation layer, a second semiconductor module and a plurality of jointing materials. The first semiconductor module has at least one first conductive structure and at least one second conductive structure. The reorientation layer covers part of the second conductive structure to form an opening. The second semiconductor module has at least one third conductive structure and at least one fourth conductive structure. The jointing materials are disposed between the first conductive structure and the third conductive structure, and disposed in the opening.

Abstract: A semiconductor device includes a semiconductor die and a conductive structure disposed side-by-side and spaced apart from each other through an insulating encapsulant. The conductive structure includes a first conductor laterally covered by the insulating encapsulant, and a second conductor disposed over and separating from the first conductor. The second conductor includes a first portion laterally covered by the insulating encapsulant and a second portion protruded from the insulating encapsulant, where a ratio of a first standoff height of the first portion and a second standoff height of the second portion ranges from about 0.4 to about 1.5.

Abstract: An electronic device and a manufacturing method thereof are provided. The method includes at least the following steps. An insulating encapsulant is formed to encapsulate a multi-layered structure and a semiconductor die, where the multi-layered structure includes a first conductor, a diffusion barrier layer on the first conductor, and a metallic layer on the diffusion barrier layer, and the insulating encapsulant at least exposes a portion of the semiconductor die and a portion of the first conductor. A redistribution structure is formed over the insulating encapsulant, the semiconductor die, and the first conductor. The metallic layer is removed to form a recess in the insulating encapsulant. A second conductor is formed in the recess over the diffusion barrier layer, where the first conductor, the diffusion barrier layer, and the second conductor form a conductive structure that is electrically coupled to the semiconductor die through the redistribution structure.

Abstract: An electronic device and a manufacturing method thereof are provided. The method includes at least the following steps. An insulating encapsulant is formed to encapsulate a multi-layered structure and a semiconductor die, where the multi-layered structure includes a first conductor, a diffusion barrier layer on the first conductor, and a metallic layer on the diffusion barrier layer, and the insulating encapsulant at least exposes a portion of the semiconductor die and a portion of the first conductor. A redistribution structure is formed over the insulating encapsulant, the semiconductor die, and the first conductor. The metallic layer is removed to form a recess in the insulating encapsulant. A second conductor is formed in the recess over the diffusion barrier layer, where the first conductor, the diffusion barrier layer, and the second conductor form a conductive structure that is electrically coupled to the semiconductor die through the redistribution structure.

Abstract: An electronic device and the manufacturing method thereof are provided. The electronic device includes a semiconductor die, a conductive structure electrically coupled to the semiconductor die, an insulating encapsulant encapsulating the semiconductor die and the conductive structure, and a redistribution structure disposed on the insulating encapsulant and the semiconductor die. The conductive structure includes a first conductor, a second conductor, and a diffusion barrier layer between the first conductor and the second conductor. The redistribution structure is electrically connected to the semiconductor die and the first conductor of the conductive structure.

Abstract: An electronic device and the manufacturing method thereof are provided. The electronic device includes a semiconductor die, a conductive structure electrically coupled to the semiconductor die, an insulating encapsulant encapsulating the semiconductor die and the conductive structure, and a redistribution structure disposed on the insulating encapsulant and the semiconductor die. The conductive structure includes a first conductor, a second conductor, and a diffusion barrier layer between the first conductor and the second conductor. The redistribution structure is electrically connected to the semiconductor die and the first conductor of the conductive structure.

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first chip, a redistribution layer structure, a plurality of connection pads, a plurality of dummy patterns, a plurality of micro-bumps, a second chip and an underfill layer. The redistribution layer structure is electrically connected to the first chip. The connection pads are electrically connected to the redistribution layer structure. The dummy patterns are at one side of the connection pads. The micro-bumps are electrically connected to the connection pads. The second chip is electrically connected to the micro-bumps. The underfill layer covers the plurality of dummy patterns and surrounds the micro-bumps.

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first chip, a redistribution layer structure, a plurality of connection pads, a plurality of dummy patterns, a plurality of micro-bumps, a second chip and an underfill layer. The redistribution layer structure is electrically connected to the first chip. The connection pads are electrically connected to the redistribution layer structure. The dummy patterns are at one side of the connection pads. The micro-bumps are electrically connected to the connection pads. The second chip is electrically connected to the micro-bumps. The underfill layer covers the plurality of dummy patterns and surrounds the micro-bumps.

Abstract: The object of the present invention is to provide a method for preparing a nano-sheet array structure of a Group V-VI semiconductor, comprising: (A) providing an electrolyte containing a hydrogen ion and disposing an auxiliary electrode and a working electrode in the electrolyte, wherein the working electrode comprises a Group V-VI semiconductor bulk; and (B) applying a redox reaction bias to the auxiliary electrode and the working electrode to form a nano-sheet array structure on the bulk.