Patents by Inventor Hung-Wei WANG
Hung-Wei WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240134968Abstract: An electronic system and a security authority delegation method thereof are provided. The electronic system includes a first host device, a second host device, a first security device, and a second security device. The first security device is connected to the first host device. The second security device is connected to the second host device and the first security device. The first security device performs an attestation process on the second security device. If the second security device passes the attestation process, the first security device enables the second security device to verify executable images of the second host device. If the second security device does not pass the attestation process, the first security device disables a function of the second security device, and the function includes verifying the executable image of the second host device.Type: ApplicationFiled: December 15, 2022Publication date: April 25, 2024Applicant: ASPEED Technology Inc.Inventors: Chin-Ting Kuo, Chia-Wei Wang, Hung Liu
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Publication number: 20240130257Abstract: Devices and method for forming a switch including a heater layer including a first heater pad, a second heater pad, and a heater line connecting the first heater pad and the second heater pad, a phase change material (PCM) layer positioned in a same vertical plane as the heater line, and a floating spreader layer including a first portion positioned in the same vertical plane as the heater line and the PCM layer, in which the first portion has a first width that is less than or equal to a distance between proximate sidewalls of the first heater pad and the second heater pad.Type: ApplicationFiled: April 21, 2023Publication date: April 18, 2024Inventors: Fu-Hai LI, Yi Ching ONG, Hsin Heng WANG, Tsung-Hao YEH, Yu-Wei TING, Kuo-Pin CHANG, Hung-Ju LI, Kuo-Ching HUANG
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Publication number: 20240084445Abstract: A leak check is performed on a semiconductor wafer processing tool that includes a process chamber and process gas lines, and a semiconductor wafer is processed using the semiconductor wafer processing tool if the leak check passes. Each gas line includes a mass flow controller (MFC) and normally closed valves including an upstream and downstream valves upstream and downstream of the MFC. Leak checking includes: leak checking up to the downstream valves of the gas lines with the upstream valves closed and the downstream valves of the gas lines closed; and leak checking up to the upstream valve of each the process gas line with the upstream valves of the of the process gas lines closed and with the downstream valve of the of the process gas line being leak checked open and the downstream valve of every other process gas line closed.Type: ApplicationFiled: January 4, 2023Publication date: March 14, 2024Inventors: Chih-Wei Chou, Yuan-Hsin Chi, Chih-Hao Yang, Hung-Chih Wang, Yu-Chi Liu, Sheng-Yuan Lin
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Publication number: 20240045820Abstract: A system on a chip (SoC) with a Universal Asynchronous Receiver/Transmitter (UART) interface includes a UART interface circuit, a detection circuit, and a control circuit. The UART interface circuit includes: a plurality of UART signal pads for receiving and transmitting signals; and a UART voltage pad for receiving an external operating voltage. The detection circuit is configured to detect the magnitude of the external operating voltage and thereby generate a detection result. The control circuit is configured to determine setting of a supply voltage for the plurality of UART signal pads according to the detection result. The control circuit makes the setting of the supply voltage be compatible with the external operating voltage according to the detection result, wherein the external operating voltage is a lower first voltage or a higher second voltage, and the first lower voltage is equal to an internal device operating voltage of the SoC.Type: ApplicationFiled: August 2, 2023Publication date: February 8, 2024Inventors: CHAO-MIN LAI, YU-JEN LIN, HUNG-WEI WANG, HUANG-LIN KUO
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Patent number: 11764676Abstract: A power supply circuit includes a first regulator and a second regulator. The first regulator is configured to generate a first output signal according to an input signal. A voltage value of the first output signal decreases according to the input signal and a first voltage threshold value at a power-off stage. The second regulator is configured to be enabled according to the first output signal to generate a second output signal according to the input signal. A voltage value of the second output signal decreases according to the input signal and a second voltage threshold value at the power-off stage. The second voltage threshold value is greater than the first voltage threshold value.Type: GrantFiled: June 25, 2021Date of Patent: September 19, 2023Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Chao-Min Lai, Chien-Liang Chen, Hung-Wei Wang, Shih-An Yang
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Publication number: 20230229203Abstract: An example computing device includes a flexible display coupled to a housing that includes a support plate having a first joint coupled to a first end of the support plate and a second joint coupled to a second end of the support plate. A slide module has a slot that guides a linear slide movement of the second joint along a linear path of movement within the slot as the support plate pivots about the first joint, where the support plate moves according to the first joint and the second joint to support at least the portion of the flexible display when the flexible display is unfolded and moves according to the first joint and the second joint to create a gap between at least a portion of the support plate and at least the portion of the flexible display when the flexible display is folded.Type: ApplicationFiled: October 29, 2020Publication date: July 20, 2023Inventors: Shih Wei Hsiang, Po-Kai Lai, Jengn Wen Lin, Hung-Wei Wang
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Patent number: 11646738Abstract: The present invention provides a processor including a core circuit, a plurality of clock signal generation circuits, a multiplexer and a detection circuit is disclosed. The core circuit is supplied by a supply voltage. The plurality of clock signal generation circuits are configured to generate a plurality of clock signals with different frequencies, respectively, wherein a number of the plurality of clock signals is equal to or greater than three. The multiplexer is configured to receive the plurality of clock signals, and to select one of the plurality of clock signals to serve as an output clock signal according to a control signal, wherein the core circuit uses the output clock signal to serve as an operating clock. The detection circuit is configured to detect a level of the supply voltage received by the core circuit in a real-time manner, to generate the control signal.Type: GrantFiled: March 15, 2022Date of Patent: May 9, 2023Assignee: Realtek Semiconductor Corp.Inventors: Chao-Min Lai, Han-Chieh Hsieh, Tang-Hung Chang, Hung-Wei Wang, Chun-Yi Kuo
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Patent number: 11579643Abstract: The present invention discloses an AVS scanning method, wherein the AVS scanning method includes the steps of: mounting a system on chip (SoC) on a printed circuit board (PCB), and connecting the SoC to a storage unit; enabling the SoC to read a boot code from the storage unit, and executing the boot code to perform an AVS scanning operation on the SoC to determine a plurality of target supply voltages respectively corresponding to a plurality of operating frequencies of the SoC to establish an AVS look-up table; and storing the AVS look-up table into the SoC or the storage unit.Type: GrantFiled: November 3, 2020Date of Patent: February 14, 2023Assignee: Realtek Semiconductor Corp.Inventors: Chao-Min Lai, Hung-Wei Wang, Tang-Hung Chang, Han-Chieh Hsieh, Chun-Yi Kuo
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Publication number: 20220416789Abstract: The present invention provides a processor including a core circuit, a plurality of clock signal generation circuits, a multiplexer and a detection circuit is disclosed. The core circuit is supplied by a supply voltage. The plurality of clock signal generation circuits are configured to generate a plurality of clock signals with different frequencies, respectively, wherein a number of the plurality of clock signals is equal to or greater than three. The multiplexer is configured to receive the plurality of clock signals, and to select one of the plurality of clock signals to serve as an output clock signal according to a control signal, wherein the core circuit uses the output clock signal to serve as an operating clock. The detection circuit is configured to detect a level of the supply voltage received by the core circuit in a real-time manner, to generate the control signal.Type: ApplicationFiled: March 15, 2022Publication date: December 29, 2022Applicant: Realtek Semiconductor Corp.Inventors: Chao-Min Lai, Han-Chieh Hsieh, Tang-Hung Chang, Hung-Wei Wang, Chun-Yi Kuo
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Publication number: 20220397943Abstract: A foldable device may include a foldable layer and a hinge mechanism. The hinge mechanism may include at least one gear module that provides for synchronized movement of the hinge mechanism about a central plane of the hinge mechanism. A lock module may be coupled the hinge mechanism. The lock module may include a cam and a plate including a plurality of recesses. The lock module may selectively lock the hinge mechanism, and the foldable device, in one of a plurality of positions, based on a position of the cam in one of the recesses.Type: ApplicationFiled: December 24, 2020Publication date: December 15, 2022Inventors: Shih-Wei Hsiang, Hung-Wei Wang, Ching-Chih Yen, Po-Kai Lai, Jeng-wen Lin
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Publication number: 20220166316Abstract: A power supply circuit includes a first regulator and a second regulator. The first regulator is configured to generate a first output signal according to an input signal. A voltage value of the first output signal decreases according to the input signal and a first voltage threshold value at a power-off stage. The second regulator is configured to be enabled according to the first output signal to generate a second output signal according to the input signal. A voltage value of the second output signal decreases according to the input signal and a second voltage threshold value at the power-off stage. The second voltage threshold value is greater than the first voltage threshold value.Type: ApplicationFiled: June 25, 2021Publication date: May 26, 2022Inventors: Chao-Min LAI, Chien-Liang Chen, Hung-Wei Wang, Shih-An Yang
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Publication number: 20220155828Abstract: A foldable device may include a foldable layer and a hinge mechanism. The hinge mechanism may include at least one synchronizing module, at least one torsion module, and a cover module. The at least one synchronizing module may include a synchronizing gear assembly including a first linking gear in meshed engagement with a first rotating link, a second linking gear in meshed engagement with a second rotating link, and at least one intermediate gear in meshed engagement with the first linking gear and the second linking gear. The first rotating link may be coupled to a first housing of a computing device and the second rotating link may be coupled to a second housing of the computing device. The meshed engagement of the first and second rotating links may provide of synchronized, symmetric movement of the first and second housings about a central axis of the computing device.Type: ApplicationFiled: December 7, 2020Publication date: May 19, 2022Inventors: Shih-Wei Hsiang, Hung-Wei Wang, Ching-Chih Yen, Po-Kai Lai, Jeng-wen Lin
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Publication number: 20210141407Abstract: The present invention discloses an AVS scanning method, wherein the AVS scanning method includes the steps of: mounting a system on chip (SoC) on a printed circuit board (PCB), and connecting the SoC to a storage unit; enabling the SoC to read a boot code from the storage unit, and executing the boot code to perform an AVS scanning operation on the SoC to determine a plurality of target supply voltages respectively corresponding to a plurality of operating frequencies of the SoC to establish an AVS look-up table; and storing the AVS look-up table into the SoC or the storage unit.Type: ApplicationFiled: November 3, 2020Publication date: May 13, 2021Inventors: Chao-Min Lai, Hung-Wei Wang, Tang-Hung Chang, Han-Chieh Hsieh, Chun-Yi Kuo
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Patent number: 10763197Abstract: An electronic apparatus and a circuit board thereof are provided. The electronic apparatus includes a control device that can operate with the circuit board, and includes a ball pad array. The ball pad array includes a plurality of power ball pads and a plurality of ground ball pads, which are arranged in the same pad arrangement region. At least a portion of the power ball pads and at least a portion of the ground ball pads are arranged in an alternate manner. The circuit board includes a solder pad array corresponding to the ball pad array of the control device so as to be disposed with the control device.Type: GrantFiled: April 1, 2019Date of Patent: September 1, 2020Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Chao-Min Lai, Hung-Wei Wang, Ping-Chia Wang
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Publication number: 20190385941Abstract: A control device and a circuit board are provided. The control device can operate with the circuit board, and includes a ball pad array. The ball pad array includes a plurality of power ball pads and a plurality of ground ball pads, which are arranged in the same pad arrangement region. At least a portion of the power ball pads and at least a portion of the ground ball pads are arranged in an alternate manner. The circuit board includes a solder pad array corresponding to the ball pad array of the control device so as to be disposed with the control device.Type: ApplicationFiled: April 1, 2019Publication date: December 19, 2019Inventors: CHAO-MIN LAI, HUNG-WEI WANG, PING-CHIA WANG
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Patent number: 9336104Abstract: A keyboard testing machine for testing a keyboard of an electronic apparatus is provided. The keyboard testing machine includes a rack, a fixing base, and a pressing module. The fixing base is operatively connected to the rack and located over the electronic apparatus. The pressing module is located over the keyboard and includes a drive shaft, a rotating member, and a pressing assembly. The drive shaft is rotatably disposed on the fixing base. The rotating member is sleeved onto the drive shaft and has a cam portion. The pressing assembly is operatively connected to the fixing base and the cam portion. When the drive shaft rotates together with the rotating member, the cam portion drives the pressing assembly to linearly move relative to the fixing base, so as to make the pressing assembly cyclically press the keyboard.Type: GrantFiled: November 1, 2013Date of Patent: May 10, 2016Assignee: QUANTA COMPUTER INC.Inventors: Lung-Chiang Chu, Hung-Wei Wang, Chin-Shun Lai
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Publication number: 20140305231Abstract: A keyboard testing machine for testing a keyboard of an electronic apparatus is apparatus. The electronic apparatus is carried on a conveyor. The keyboard testing machine includes a rack, a 3D movement apparatus, a linear encoder, a first driving module, and a pressing module. A first slide rail of the rack is parallel to the conveying direction of the conveyor. The 3D movement apparatus is slidably disposed on the first slide rail. The linear encoder is used to detect the conveying speed of the conveyor. The first driving module is disposed on the rack for driving the 3D movement apparatus to move along the first slide rail with the conveying speed. The pressing module is operatively connected to the 3D movement apparatus. The 3D movement apparatus makes the pressing module press the keyboard, and moves the pressing module along a pressing path relative to the keyboard.Type: ApplicationFiled: November 1, 2013Publication date: October 16, 2014Applicant: Quanata Computer Inc.Inventors: Lung-Chiang CHU, Hung-Wei WANG, Chin-Shun LAI
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Publication number: 20140283629Abstract: A keyboard testing machine for testing a keyboard of an electronic apparatus is provided. The keyboard testing machine includes a rack, a fixing base, and a pressing module. The fixing base is operatively connected to the rack and located over the electronic apparatus. The pressing module is located over the keyboard and includes a drive shaft, a rotating member, and a pressing assembly. The drive shaft is rotatably disposed on the fixing base. The rotating member is sleeved onto the drive shaft and has a cam portion. The pressing assembly is operatively connected to the fixing base and the cam portion. When the drive shaft rotates together with the rotating member, the cam portion drives the pressing assembly to linearly move relative to the fixing base, so as to make the pressing assembly cyclically press the keyboard.Type: ApplicationFiled: November 1, 2013Publication date: September 25, 2014Applicant: Quanta Computer Inc.Inventors: Lung-Chiang CHU, Hung-Wei WANG, Chin-Shun LAI
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Patent number: D1018537Type: GrantFiled: November 7, 2023Date of Patent: March 19, 2024Assignee: HTC CORPORATIONInventors: Shu-Kuen Chang, Natalia Amijo, Ian James McGillivray, Chin-Wei Chou, Yi-Shen Wang, Chih-Sung Fang, Hung-Yu Chen