Patents by Inventor Hung-Wei Yu
Hung-Wei Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11963295Abstract: Provided are a circuit apparatus, a manufacturing method thereof, and a circuit system. The circuit apparatus includes a flexible circuit board, a flexible packaging material layer and an electronic device. The flexible circuit board has at least one hollow pattern, wherein the flexible circuit board has an inner region and a peripheral region surrounding the inner region, and has a first surface and a second surface opposite to each other. The flexible packaging material layer is disposed in the at least one hollow pattern. The electronic device is disposed on the first surface of the flexible circuit board and electrically connected with the flexible circuit board.Type: GrantFiled: January 27, 2022Date of Patent: April 16, 2024Assignee: Industrial Technology Research InstituteInventors: Hung-Hsien Ko, Yi-Cheng Lu, Heng-Yin Chen, Hao-Wei Yu, Te-Hsun Lin
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Publication number: 20220367176Abstract: Methods and structures includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure. Thereby structures are formed.Type: ApplicationFiled: July 26, 2022Publication date: November 17, 2022Inventors: Hung-Wei Yu, Yi Chang, Tsun-Ming Wang
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Patent number: 11437235Abstract: Methods and structures includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure. Thereby structures are formed.Type: GrantFiled: November 10, 2020Date of Patent: September 6, 2022Assignee: Taiwan Semiconductor Manufacturing Company Limited & National Chiao-Tung UniversityInventors: Hung-Wei Yu, Yi Chang, Tsun-Ming Wang
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Publication number: 20210057211Abstract: Methods and structures includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure. Thereby structures are formed.Type: ApplicationFiled: November 10, 2020Publication date: February 25, 2021Inventors: Hung-Wei Yu, Yi Chang, Tsun-Ming Wang
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Patent number: 10854446Abstract: Methods and structures includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure. Thereby structures are formed.Type: GrantFiled: August 13, 2018Date of Patent: December 1, 2020Assignees: Taiwan Semiconductor Manufacturing Company Limited, National Chiao-Tung UniversityInventors: Hung-Wei Yu, Yi Chang, Tsun-Ming Wang
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Publication number: 20190006173Abstract: Methods and structures includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure. Thereby structures are formed.Type: ApplicationFiled: August 13, 2018Publication date: January 3, 2019Inventors: Hung-Wei Yu, Yi Chang, Tsun-Ming Wang
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Patent number: 10049872Abstract: A method includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure.Type: GrantFiled: March 8, 2016Date of Patent: August 14, 2018Assignee: Taiwan Semiconductor Manufacturing Company Limited & National Chiao-Tung UniversityInventors: Hung-Wei Yu, Yi Chang, Tsun-Ming Wang
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Publication number: 20160189952Abstract: A method includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure.Type: ApplicationFiled: March 8, 2016Publication date: June 30, 2016Inventors: HUNG-WEI YU, YI CHANG, TSUN-MING WANG
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Patent number: 9287122Abstract: Disclosed is a method of providing a chemical compound semiconductor channel layer on a substrate for use in a semiconductor fabrication process. The method comprises providing a prelayer over a substrate, providing a barrier layer over the prelayer, and providing an InAs or Sb-based channel layer over the barrier layer. The substrate comprises a gallium arsenide substrate, a silicon substrate, a germanium substrate, or a Ge/Si substrate. The prelayer comprises a graded-temperature arsenic prelayer grown with graded temperature ramped from 300 to 550° C. The barrier layer comprises GaAs with low-growth-temperature growth or an InxGa1-xAs epitaxy with one or multiple GaAs-based layers. The channel layer comprises an InAs epitaxy with low-growth-temperature growth or Al(In)Sb/InAs/Al(In)Sb heterostructures with one or more pairs.Type: GrantFiled: August 6, 2014Date of Patent: March 15, 2016Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hung-Wei Yu, Yi Chang, Tsun-Ming Wang
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Publication number: 20150262810Abstract: Disclosed is a method of providing a chemical compound semiconductor channel layer on a substrate for use in a semiconductor fabrication process. The method comprises providing a prelayer over a substrate, providing a barrier layer over the prelayer, and providing an InAs or Sb-based channel layer over the barrier layer. The substrate comprises a gallium arsenide substrate, a silicon substrate, a germanium substrate, or a Ge/Si substrate. The prelayer comprises a graded-temperature arsenic prelayer grown with graded temperature ramped from 300 to 550° C. The barrier layer comprises GaAs with low-growth-temperature growth or an InxGa1-xAs epitaxy with one or multiple GaAs-based layers. The channel layer comprises an InAs epitaxy with low-growth-temperature growth or Al(In)Sb/InAs/Al(In)Sb heterostructures with one or more pairs.Type: ApplicationFiled: August 6, 2014Publication date: September 17, 2015Inventors: HUNG-WEI YU, YI CHANG, TSUN-MING WANG
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Publication number: 20130148296Abstract: The present invention discloses a protecting jacket, which includes a protecting jacket body and a semiconductor cooler. The semiconductor cooler is disposed on an inner surface of the protecting jacket body. The semiconductor cooler includes a Peltier element, a thermistor sensor, a PWM controller, and a switching element. The PWM controller is respectively coupled to the thermistor sensor and the switching element, and the switching element is coupled to the Peltier element. A circuit is connected by the switching element for making the semiconductor cooler work when a temperature of an electronic product is higher than a constant value. In distinct contrast, the circuit is disconnected by the switching element for stopping the semiconductor cooler working when the temperature of the electronic product is lower than the constant value. Therefore, the electronic product can maintain a longer working time, and conserving energy is achieved.Type: ApplicationFiled: December 13, 2011Publication date: June 13, 2013Applicant: Cheng Uei Precision Industry Co., LTD.Inventors: CHI-HAN HUANG, Chi-yuan Lee, Hung-wei Yu
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Patent number: 7990077Abstract: A LED control circuit includes an LED array circuit and a control circuit. The LED array circuit has a plurality of parallel branches, each of which has a constant-current regulator, an LED and an FET connected together in series, wherein the constant-current regulator supplies a steady current to the corresponding LED and the FET can control the respective LED to be put out or lighted up. The control circuit includes a microprocessor and a temperature sensor. The temperature sensor is connected with the microprocessor and located near the LEDs of the LED array circuit for detecting the temperature of the LEDs and transmitting the temperature signals to the microprocessor. The microprocessor is connected with the FETs of the LED array circuit for controlling the corresponding FETs to be repeatedly on or off according to the temperature signals in order to regulate the temperature of the corresponding LEDs respectively.Type: GrantFiled: December 12, 2008Date of Patent: August 2, 2011Assignee: Cheng Uei Precision Industry Co., Ltd.Inventors: Hung-Wei Yu, Hsin-Wei Chen
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Publication number: 20100148701Abstract: A LED control circuit includes an LED array circuit and a control circuit. The LED array circuit has a plurality of parallel branches, each of which has a constant-current regulator, an LED and an FET connected together in series, wherein the constant-current regulator supplies a steady current to the corresponding LED and the FET can control the respective LED to be put out or lighted up. The control circuit includes a microprocessor and a temperature sensor. The temperature sensor is connected with the microprocessor and located near the LEDs of the LED array circuit for detecting the temperature of the LEDs and transmitting the temperature signals to the microprocessor. The microprocessor is connected with the FETs of the LED array circuit for controlling the corresponding FETs to be repeatedly on or off according to the temperature signals in order to regulate the temperature of the corresponding LEDs respectively.Type: ApplicationFiled: December 12, 2008Publication date: June 17, 2010Inventors: Hung-Wei Yu, Hsin-Wei Chen