Patents by Inventor Hung-Wen Lin

Hung-Wen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240121722
    Abstract: An example device is to monitor communications throughput rates and select modulation and coding protocols in order to minimize specific absorption rates experienced by users of the devices by minimizing or reducing transmission power settings.
    Type: Application
    Filed: March 12, 2021
    Publication date: April 11, 2024
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: I-Chen Lin, Chung-Chun Chen, Cheng-Fang Lin, Hung-Wen Cheng, Isaac Lagnado, Leo Joseph Gerten
  • Publication number: 20240102154
    Abstract: A vacuum processing apparatus (110) for deposition of a material on a substrate is provided. The vacuum processing apparatus (110) includes a vacuum chamber comprising a processing area (111); a deposition apparatus (112) within the processing area (111) of the vacuum chamber; a cooling surface (113) inside the vacuum chamber; and one or more movable shields (220) between the cooling surface (113) and the processing area (111).
    Type: Application
    Filed: February 24, 2020
    Publication date: March 28, 2024
    Inventors: Chun Cheng CHEN, Hung-Wen CHANG, Shin-Hung LIN, Chi-Chang YANG, Christoph MUNDORF, Thomas GEBELE, Jürgen GRILLMAYER
  • Publication number: 20240070416
    Abstract: A reading method and a reading device for a two-dimensional code. The method includes: capturing a two-dimensional code image through an image capturing device; detecting an outer frame and a position mark of a two-dimensional code in a skewed state in the two-dimensional code image; restoring the two-dimensional code in the skewed state to a default state; and performing a default operation according to the two-dimensional code in the default state.
    Type: Application
    Filed: November 15, 2022
    Publication date: February 29, 2024
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Chin-Hao Yeh, Chin-Wen Lin, Hung-Yi Lin
  • Patent number: 11914429
    Abstract: An electronic device includes a host, a display, a sliding plate, and a keyboard. The host has an operating surface. The display is pivoted to the host. The sliding plate is slidably disposed in the host, where the display is mechanically coupled to the sliding plate, and the sliding plate includes a plat portion and a recess portion that are arranged side by side. The keyboard is integrated to the host. The keyboard includes a key structure, where the key structure includes a key cap and a reciprocating element, and the key cap is exposed from the operating surface of the host. The reciprocating element is disposed between the key cap and the sliding plate and has a first end connected to the key cap and a second end contacting the sliding plate. The second end is located on a sliding path of the plat portion and the recess portion.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: February 27, 2024
    Assignee: Acer Incorporated
    Inventors: Hung-Chi Chen, Shun-Bin Chen, Huei-Ting Chuang, Yen-Chieh Chiu, Yu-Wen Lin, Yen-Chou Chueh, Po-Yi Lee
  • Patent number: 11744045
    Abstract: An electronic device that includes a first device portion, a second device portion coupled to the first device portion; and a thermally conductive connector coupled to the first device portion and the second device portion, wherein the thermally conductive connector includes a graphite sheet. The first device portion includes a region that includes a component configured to generate heat.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: August 29, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Hung-Wen Lin, Sin-Shong Wang, Jen-Chun Chang, Qiang Du, Jorge Luis Rosales, Ajit Kumar Vallabhaneni
  • Patent number: 11733749
    Abstract: An electronic device that includes a first device portion, a second device portion coupled to the first device portion, and a uni-directional thermally conductive connector coupled to the first device portion and the second device portion. The first device portion comprises a region that includes a component configured to generate heat. The uni-directional thermally conductive connector is configured to dissipate heat away from the first device portion and towards the second device portion. The uni-directional thermally conductive connector includes a thermally conductive material that primarily dissipates heat along a first direction of the thermally conductive material.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: August 22, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Hung-Wen Lin, Sin-Shong Wang, Keith Wang, Ajit Kumar Vallabhaneni, Jen-Chun Chang
  • Publication number: 20230145773
    Abstract: An electronic device that includes a first device portion, a second device portion coupled to the first device portion; and a thermally conductive connector coupled to the first device portion and the second device portion, wherein the thermally conductive connector includes a graphite sheet. The first device portion includes a region that includes a component configured to generate heat.
    Type: Application
    Filed: November 10, 2021
    Publication date: May 11, 2023
    Inventors: Hung-Wen LIN, Sin-Shong WANG, Jen-Chun CHANG, Qiang DU, Jorge Luis ROSALES, Ajit Kumar VALLABHANENI
  • Patent number: 11637051
    Abstract: An assembly comprising a substrate, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, a frame coupled to the substrate such that the frame at least partially surrounds the first integrated device and the second integrated device, and a step heat sink coupled to the frame, such that the step heat sink is located over the first integrated device and the second integrated device. The assembly may further include a shield coupled to the frame such that the shield is located between the frame and the step heat sink. The shield may include a step shield. The assembly may further include a heat pipe coupled to the step heat sink.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: April 25, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Hung-Wen Lin, Sin-Shong Wang, Jen-Chun Chang, Ajit Kumar Vallabhaneni, Keith Wang
  • Patent number: 11302664
    Abstract: A method of manufacturing a die package structure includes steps described below. A conductive substrate with a plurality of trenches is provided. A die is disposed in each of the trenches. A conductive layer is formed covering the dies and the conductive substrate. A patterned photoresist layer with a plurality of openings is formed exposing a plurality of areas of the conductive layer. A mask is formed on each of the areas of the conductive layer. The patterned photoresist layer is removed after forming the masks. By using the masks, the conductive layer and the conductive substrate under thereof are selectively etched to a predetermined depth to form a plurality of conductive bumps and a plurality of electrodes, in which a remaining of the conductive substrate includes a bottom substrate, the electrodes and the conductive bumps. An upper sealing layer is formed covering the bottom substrate and the dies.
    Type: Grant
    Filed: May 31, 2020
    Date of Patent: April 12, 2022
    Assignee: Comchip Technology Co., Ltd.
    Inventors: Chien-Chih Lai, Hung-Wen Lin
  • Patent number: 11264355
    Abstract: A method of manufacturing a die package structure includes steps described below. A conductive substrate with a plurality of trenches is provided. A die is disposed in each of the trenches. A conductive layer is formed covering the dies and the conductive substrate. A patterned photoresist layer with a plurality of openings is formed exposing a plurality of areas of the conductive layer. A mask is formed on each of the areas of the conductive layer. The patterned photoresist layer is removed after forming the masks. By using the masks, the conductive layer and the conductive substrate under thereof are selectively etched to a predetermined depth to form a plurality of conductive bumps and a plurality of electrodes, in which a remaining of the conductive substrate includes a bottom substrate, the electrodes and the conductive bumps. An upper sealing layer is formed covering the bottom substrate and the dies.
    Type: Grant
    Filed: May 17, 2020
    Date of Patent: March 1, 2022
    Assignee: Comchip Technology Co., Ltd.
    Inventors: Chien-Chih Lai, Hung-Wen Lin
  • Publication number: 20220006531
    Abstract: The present application provides an optical network method and associated apparatus. The method includes: receiving uplink burst time assignment information; and enabling or disabling a laser module of a local end according to the uplink burst time assignment information.
    Type: Application
    Filed: May 25, 2021
    Publication date: January 6, 2022
    Inventors: HUNG-WEN LIN, MU-JUNG HSU
  • Publication number: 20210397928
    Abstract: A device, a method and a storage medium for accelerating activation function in relation to data processing by artificial neural network provides a register for storing a storage table, a matching unit including a plurality of comparators, a logic unit, and a selection unit. The comparators compare an input variable of the activation function with the variable intervals of the activation function to obtain a comparison output result, the logic unit performs a logical operation according to the comparison output result to obtain a logic output result and determines a variable interval to be calculated according to the logic output. The selection unit queries the storage table according to the variable interval to be calculated and obtains parameters of fitted quadratic function. A calculation unit performs calculations on the input variable according to the parameters.
    Type: Application
    Filed: June 22, 2021
    Publication date: December 23, 2021
    Inventors: TA-WEI CHAN, HUNG-WEN LIN
  • Publication number: 20210373628
    Abstract: An electronic device that includes a first device portion, a second device portion coupled to the first device portion, and a uni-directional thermally conductive connector coupled to the first device portion and the second device portion. The first device portion comprises a region that includes a component configured to generate heat. The uni-directional thermally conductive connector is configured to dissipate heat away from the first device portion and towards the second device portion. The uni-directional thermally conductive connector includes a thermally conductive material that primarily dissipates heat along a first direction of the thermally conductive material.
    Type: Application
    Filed: November 10, 2020
    Publication date: December 2, 2021
    Inventors: Hung-Wen LIN, Sin-Shong WANG, Keith WANG, Ajit Kumar VALLABHANENI, Jen-Chun CHANG
  • Publication number: 20210343672
    Abstract: A method of manufacturing a die package structure includes steps described below. A conductive substrate with a plurality of trenches is provided. A die is disposed in each of the trenches. A conductive layer is formed covering the dies and the conductive substrate. A patterned photoresist layer with a plurality of openings is formed exposing a plurality of areas of the conductive layer. A mask is formed on each of the areas of the conductive layer. The patterned photoresist layer is removed after forming the masks. By using the masks, the conductive layer and the conductive substrate under thereof are selectively etched to a predetermined depth to form a plurality of conductive bumps and a plurality of electrodes, in which a remaining of the conductive substrate includes a bottom substrate, the electrodes and the conductive bumps. An upper sealing layer is formed covering the bottom substrate and the dies.
    Type: Application
    Filed: May 31, 2020
    Publication date: November 4, 2021
    Inventors: Chien-Chih LAI, Hung-Wen LIN
  • Publication number: 20210265304
    Abstract: A method of manufacturing a die package structure includes steps described below. A conductive substrate with a plurality of trenches is provided. A die is disposed in each of the trenches. A conductive layer is formed covering the dies and the conductive substrate. A patterned photoresist layer with a plurality of openings is formed exposing a plurality of areas of the conductive layer. A mask is formed on each of the areas of the conductive layer. The patterned photoresist layer is removed after forming the masks. By using the masks, the conductive layer and the conductive substrate under thereof are selectively etched to a predetermined depth to form a plurality of conductive bumps and a plurality of electrodes, in which a remaining of the conductive substrate includes a bottom substrate, the electrodes and the conductive bumps. An upper sealing layer is formed covering the bottom substrate and the dies.
    Type: Application
    Filed: May 17, 2020
    Publication date: August 26, 2021
    Inventors: Chien-Chih LAI, Hung-Wen LIN
  • Patent number: 11026003
    Abstract: Disclosed is an optical network unit (ONU) capable of reporting current Dynamic Bandwidth Report upstream (DBRu) information to an optical line terminal (OLT) according to the amount variation of to-be-transmitted upstream data in a buffer. The ONU includes: the buffer temporarily storing the to-be-transmitted upstream data; a register circuit recording previous data amount information related to the previous data amount of the buffer at a previous time point earlier than a current time point; a DBRu information generating circuit generating the current DBRu information according to an amount difference and a current data amount of the buffer at the current time point, wherein the amount difference is dependent on the difference between the previous data amount information and current data amount information that is dependent on the current data amount; and a transmitting circuit transmitting the current DBRu information to the OLT.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: June 1, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hung-Wen Lin, Mu-Jung Hsu
  • Publication number: 20210118764
    Abstract: An assembly comprising a substrate, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, a frame coupled to the substrate such that the frame at least partially surrounds the first integrated device and the second integrated device, and a step heat sink coupled to the frame, such that the step heat sink is located over the first integrated device and the second integrated device. The assembly may further include a shield coupled to the frame such that the shield is located between the frame and the step heat sink. The shield may include a step shield. The assembly may further include a heat pipe coupled to the step heat sink.
    Type: Application
    Filed: October 8, 2020
    Publication date: April 22, 2021
    Inventors: Hung-Wen LIN, Sin-Shong WANG, Jen-Chun CHANG, Ajit Kumar VALLABHANENI, Keith WANG
  • Patent number: 10950502
    Abstract: A method for manufacturing chip package is disclosed. The method includes providing a wafer having conductive bumps disposed on a first surface; forming a first adhesion layer and a first carrier board; thinning the wafer; forming a first insulating layer; forming a second adhesion layer and a second carrier board; heating the first adhesion layer to a first temperature to remove the first carrier board and the first adhesion layer; forming trenches; forming a third adhesion layer and a third carrier board; heating the second adhesion layer to a second temperature to remove the second carrier board and the second adhesion layer; forming a second insulating layer filling the trenches; heating the third adhesion layer to a third temperature to remove the third carrier board and the third adhesion layer; and dicing the first insulating layer and the second insulating layer along each trench.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: March 16, 2021
    Assignee: Comchip Technology Co., Ltd.
    Inventors: Chien-Chih Lai, Hung-Wen Lin
  • Patent number: 10937760
    Abstract: A method for manufacturing chip package is disclosed. The method includes providing a wafer having an upper surface and a lower surface opposite thereto, in which the wafer comprises a plurality of conductive pads disposed on the upper surface; dicing the upper surface of the wafer to form a plurality of trenches; forming a patterned photoresist layer on the upper surface and in the trenches; forming a plurality of conductive bumps disposed correspondingly on the conductive pads; thinning the wafer from the lower surface toward the upper surface, such that the patterned photoresist layer in the trenches is exposed from the lower surface; forming an insulating layer under the lower surface; and dicing the patterned photoresist layer and the insulating layer along each trench to form a plurality of chip packages.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: March 2, 2021
    Assignee: COMCHIP TECHNOLOGY CO., LTD.
    Inventors: Chien-Chih Lai, Hung-Wen Lin
  • Publication number: 20210037300
    Abstract: Disclosed is an optical network unit (ONU) capable of reporting current Dynamic Bandwidth Report upstream (DBRu) information to an optical line terminal (OLT) according to the amount variation of to-be-transmitted upstream data in a buffer. The ONU includes: the buffer temporarily storing the to-be-transmitted upstream data; a register circuit recording previous data amount information related to the previous data amount of the buffer at a previous time point earlier than a current time point; a DBRu information generating circuit generating the current DBRu information according to an amount difference and a current data amount of the buffer at the current time point, wherein the amount difference is dependent on the difference between the previous data amount information and current data amount information that is dependent on the current data amount; and a transmitting circuit transmitting the current DBRu information to the OLT.
    Type: Application
    Filed: July 22, 2020
    Publication date: February 4, 2021
    Inventors: HUNG-WEN LIN, MU-JUNG HSU