Patents by Inventor Hung-Wen Lu
Hung-Wen Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136117Abstract: A multi-phase coupled inductor includes a first iron core, a second iron core, and a plurality of coil windings. The first iron core includes a first body and a plurality of first core posts. The plurality of first core posts are connected to the first body. The second iron core is opposite to the first iron core. The second iron core and the first body are spaced apart from each other by a gap. The plurality of coil windings wrap around the plurality of first core posts, respectively. Each of the coil windings has at least two coils.Type: ApplicationFiled: October 1, 2023Publication date: April 25, 2024Inventors: HUNG-CHIH LIANG, PIN-YU CHEN, HANG-CHUN LU, YA-WEN YANG, YU-TING HSU, WEI-ZHI HUANG
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Publication number: 20240088187Abstract: Trenches in which to form a back side isolation structure for an array of CMOS image sensors are formed by a cyclic process that allows the trenches to be kept narrow. Each cycle of the process includes etching to add a depth segment to the trenches and coating the depth segment with an etch-resistant coating. The following etch step will break through the etch-resistant coating at the bottom of the trench but the etch-resistant coating will remain in the upper part of the trench to limit lateral etching and substrate damage. The resulting trenches have a series of vertically spaced nodes. The process may result in a 10% increase in photodiode area and a 30-40% increase in full well capacity.Type: ApplicationFiled: January 3, 2023Publication date: March 14, 2024Inventors: Chih Cheng Shih, Tsun-Kai Tsao, Jiech-Fun Lu, Hung-Wen Hsu, Bing Cheng You, Wen-Chang Kuo
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Patent number: 11916091Abstract: A backside illumination (BSI) image sensor and a method of forming the same are provided. A device includes a substrate and a plurality of photosensitive regions in the substrate. The substrate has a first side and a second side opposite to the first side. The device further includes an interconnect structure on the first side of the substrate, and a plurality of recesses on the second side of the substrate. The plurality of recesses extend into a semiconductor material of the substrate.Type: GrantFiled: April 15, 2021Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Wen Hsu, Jiech-Fun Lu, Yeur-Luen Tu, U-Ting Chen, Shu-Ting Tsai, Hsiu-Yu Cheng
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Patent number: 10499474Abstract: A driver circuit and a driving method with low inrush current are provided. The driving method includes steps of: supplying a charging current smaller than a high inrush current; outputting a pulse signal from a pulse generating circuit; enabling a light driving circuit to receive the charging current by the pulse signal and allowing the charging current to flow to an storage capacitor; turning on a switch component and a light-emitting assembly by the pulse signal; supplying an auxiliary current smaller than the high inrush current; enabling the light driving circuit to receive the auxiliary current and allowing auxiliary current to flow sequentially to the switch component and the light-emitting assembly; and emitting light by the light-emitting assembly with the discharging current of the storage capacitor and the auxiliary current of input power source.Type: GrantFiled: February 20, 2019Date of Patent: December 3, 2019Assignee: ANPEC ELECTRONICS CORPORATIONInventors: Chih-Ning Chen, Chih-Heng Su, Hung-Wen Lu
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Patent number: 7977993Abstract: A signal delay circuit including a capacitive load element is described. The capacitive load element has a first input end, a second input end, and a third input end. The first input end receives a first signal, the second input end receives a second signal inverted to the first signal, and the third input end receives a control signal. The capacitance of the capacitive load element changes with the control signal.Type: GrantFiled: May 20, 2008Date of Patent: July 12, 2011Assignee: Industrial Technology Research InstituteInventors: Hung-Wen Lu, Chau-Chin Su
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Patent number: 7912166Abstract: A jitter measurement circuit and a method for calibrating the jitter measurement circuit are disclosed. The jitter measurement circuit includes a synchronous dual-phase detector and a decision circuit. In a test mode, a probability distribution function (PDF) of the jitter of a clock signal output by a circuit under test is obtained. In a calibration mode, a random clock, which is externally generated or generated by a free-run oscillator in the circuit under test, is used to calibrate the synchronous dual-phase detector. The decision circuit performs logic operations, data latching and counting on a phase relationship detected by the synchronous dual-phase detector in order to obtain a counting value and a PDF relative to the jitter of the clock signal.Type: GrantFiled: October 10, 2007Date of Patent: March 22, 2011Assignee: Faraday Technology Corp.Inventors: Jen-Chien Hsu, Hung-Wen Lu, Chau-Chin Su, Yeong-Jar Chang
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Patent number: 7843276Abstract: An oscillation circuit induces a first inverter, a second inverter, a first inductive load, a second inductive load and a capacitive load. A first inverter and a second inverter receive a first signal and a second signal, and invert the first and the second signal to output a first inverted signal and a second inverted signal respectively. An output end of the first inverter is electrically connected to a first inductive load, and an output end of the second inverter is electrically connected to a second inductive load. Further, a capacitive load is electrically connected to the output end of the first inverter and the output end of the second inverter, so as to receive the first and the second inverted signal respectively. The capacitance of the capacitive load changes with a control signal.Type: GrantFiled: August 18, 2008Date of Patent: November 30, 2010Assignee: Industrial Technology Research InstituteInventors: Hung-Wen Lu, Chau-Chin Su
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Patent number: 7764086Abstract: A buffer circuit having an input terminal and an output terminal comprises a first inverter having an input node coupled to the input terminal and an output node coupled to the output terminal, a second inverter having an input node coupled to a reference voltage and an output node, a third inverter having an input node coupled to the output terminal and an output node coupled to the output node of the second inverter, a fourth inverter having an input node coupled to the output node of the second inverter and an output node coupled to the output terminal, a fifth inverter having an input node and an output node coupled to the output terminal, a sixth inverter having an input node and an output node coupled to the output node of the second inverter, a first resistive element is coupled between the output terminal and the input node of the fifth inverter, and a second resistive element is coupled between the output node of the second inverter and the input node of the sixth inverter.Type: GrantFiled: September 10, 2007Date of Patent: July 27, 2010Assignee: Industrial Technology Research InstituteInventors: Hung Wen Lu, Chauchin Su
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Publication number: 20090167399Abstract: A signal delay circuit including a capacitive load element is described. The capacitive load element has a first input end, a second input end, and a third input end. The first input end receives a first signal, the second input end receives a second signal inverted to the first signal, and the third input end receives a control signal. The capacitance of the capacitive load element changes with the control signal.Type: ApplicationFiled: May 20, 2008Publication date: July 2, 2009Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Hung-Wen LU, Chau-Chin SU
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Publication number: 20090096439Abstract: A jitter measurement circuit and a method for calibrating the jitter measurement circuit are disclosed. The jitter measurement circuit includes a synchronous dual-phase detector and a decision circuit. In a test mode, a probability distribution function (PDF) of the jitter of a clock signal output by a circuit under test is obtained. In a calibration mode, a random clock, which is externally generated or generated by a free-run oscillator in the circuit under test, is used to calibrate the synchronous dual-phase detector. The decision circuit performs logic operations, data latching and counting on a phase relationship detected by the synchronous dual-phase detector in order to obtain a counting value and a PDF relative to the jitter of the clock signal.Type: ApplicationFiled: October 10, 2007Publication date: April 16, 2009Applicant: FARADAY TECHNOLOGY CORP.Inventors: Jen-Chien Hsu, Hung-Wen Lu, Chau-Chin Su, Yeong-Jar Chang
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Publication number: 20090072869Abstract: Disclosed is a sample and hold circuit for detecting a parameter of a data signal, which includes: a first switching module, wherein the sample and hold circuit samples the data signal according to the turning on or off of the first switching module; at least one capacitor, coupled to the first switching module; a second switching module, coupled to the capacitor; a controllable reference voltage source, for providing a first reference voltage to charge/discharge the capacitor via the second switching module according to a control signal; a first comparator, coupled to the capacitor, for comparing a voltage drop on the capacitor and the first reference voltage to generate a first comparing result; and a control circuit, coupled to the controllable reference voltage source and the first comparator, for generating the control signal according to the comparing results.Type: ApplicationFiled: September 13, 2007Publication date: March 19, 2009Inventors: Jen-Chien Hsu, Hung-Wen Lu, Chau-Chin Su, Yeong-Jar Chang
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Patent number: 7495479Abstract: Disclosed is a sample and hold circuit for detecting a parameter of a data signal, which includes: a first switching module, wherein the sample and hold circuit samples the data signal according to the turning on or off of the first switching module; at least one capacitor, coupled to the first switching module; a second switching module, coupled to the capacitor; a controllable reference voltage source, for providing a first reference voltage to charge/discharge the capacitor via the second switching module according to a control signal; a first comparator, coupled to the capacitor, for comparing a voltage drop on the capacitor and the first reference voltage to generate a first comparing result; and a control circuit, coupled to the controllable reference voltage source and the first comparator, for generating the control signal according to the comparing results.Type: GrantFiled: September 13, 2007Date of Patent: February 24, 2009Assignee: Faraday Technology Corp.Inventors: Jen-Chien Hsu, Hung-Wen Lu, Chau-Chin Su, Yeong-Jar Chang
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Patent number: 7474239Abstract: In a precisely self-calibrating high-speed analog to digital converter the aspect ratios of tri-state inverters are adjusted to fine-tune threshold voltage as comparators. And the multiplexers composed of tri-state inverters amplify the signal from the output of comparators. Their switches of tri-state inverters may be properly controlled to select the optimal channels and reduce unnecessary power consumption. The calibration circuitry utilizes under-sampling to calculate the duty cycles of comparators, selecting the optimal comparators and channels. By the way, the invention may avoid process variation.Type: GrantFiled: July 9, 2007Date of Patent: January 6, 2009Assignee: National Chiao Tung UniversityInventors: Chau-Chin Su, Hung-Wen Lu, Shun-Min Chi
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Publication number: 20080315966Abstract: An oscillation circuit induces a first inverter, a second inverter, a first inductive load, a second inductive load and a capacitive load. A first inverter and a second inverter receive a first signal and a second signal, and invert the first and the second signal to output a first inverted signal and a second inverted signal respectively. An output end of the first inverter is electrically connected to a first inductive load, and an output end of the second inverter is electrically connected to a second inductive load. Further, a capacitive load is electrically connected to the output end of the first inverter and the output end of the second inverter, so as to receive the first and the second inverted signal respectively. The capacitance of the capacitive load changes with a control signal.Type: ApplicationFiled: August 18, 2008Publication date: December 25, 2008Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Hung-Wen Lu, Chau-Chin Su
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Patent number: 7415089Abstract: A system for clock and data recovery (“CDR”) includes a clock generator, a half-rate phase detector for receiving the input data, an encoder, a phase selector outputting recovered clock, a confidence counter, and a multiplexer outputting recovered data. The clock generator generates an 8-phase clock signal at half a rate of the transmitted serial data. The phase detector samples input data at four times the standard sampling rate, takes the oversampled data and detects phase transitions therein, i.e., phase lead and lag. The encoder encodes the phase transition data. The confidence counter receives the phase transition data and generates a signal representing the accumulated net effect of the phase transitions. The phase selector receives the confidence counter signal and the 8-phase clock from the clock generator, and determines the optimum phase for data sampling.Type: GrantFiled: March 16, 2004Date of Patent: August 19, 2008Assignee: Industrial Technology Research InstituteInventors: Chau-chin Su, Chien-Hsi Lee, Hung-Wen Lu, Hsueh-Chin Lin, Yen-Pin Tseng, Chia-Nan Wang, Uan-Jiun Liu
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Publication number: 20080180289Abstract: A precisely self-calibrating high-speed analog to digital converter is disclosed, wherein the aspect ratios of tri-state inverters are adjusted to fine-tune threshold voltage as comparators. And the multiplexers composed of tri-state inverters amplify the signal from the output of comparators. Their switches of tri-state inverters may be properly controlled to select the optimal channels and reduce unnecessary power consumption. The calibration circuitry utilizes under-sampling to calculate the duty cycles of comparators, selecting the optimal comparators and channels. By the way, the invention may avoid process variation.Type: ApplicationFiled: July 9, 2007Publication date: July 31, 2008Applicant: NATIONAL CHIAO TUNG UNIVERSITYInventors: CHAU-CHIN SU, HUNG-WEN LU, SHUN-MIN CHI
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Publication number: 20080150583Abstract: A buffer circuit having an input terminal and an output terminal comprises a first inverter having an input node coupled to the input terminal and an output node coupled to the output terminal, a second inverter having an input node coupled to a reference voltage and an output node, a third inverter having an input node coupled to the output terminal and an output node coupled to the output node of the second inverter, a fourth inverter having an input node coupled to the output node of the second inverter and an output node coupled to the output terminal, a fifth inverter having an input node and an output node coupled to the output terminal, a sixth inverter having an input node and an output node coupled to the output node of the second inverter, a first resistive element is coupled between the output terminal and the input node of the fifth inverter, and a second resistive element is coupled between the output node of the second inverter and the input node of the sixth inverter.Type: ApplicationFiled: September 10, 2007Publication date: June 26, 2008Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Hung Wen LU, Chauchin SU
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Publication number: 20050207520Abstract: A system for clock and data recovery (“CDR”) includes a clock generator, a half-rate phase detector for receiving the input data, an encoder, a phase selector outputting recovered clock, a confidence counter, and a multiplexer outputting recovered data. The clock generator generates an 8-phase clock signal at half a rate of the transmitted serial data. The phase detector samples input data at four times the standard sampling rate, takes the oversampled data and detects phase transitions therein, i.e., phase lead and lag. The encoder encodes the phase transition data. The confidence counter receives the phase transition data and generates a signal representing the accumulated net effect of the phase transitions. The phase selector receives the confidence counter signal and the 8-phase clock from the clock generator, and determines the optimum phase for data sampling.Type: ApplicationFiled: March 16, 2004Publication date: September 22, 2005Inventors: Chau-chin Su, Chien-Hsi Lee, Hung-Wen Lu, Hsueh-Chin Lin, Yen-Pin Tseng, Chia-Nan Wang, Uan-Jiun Liu