Abstract: System for free-space light coupling between 2-dimensional light transmitter and receiver arrays using flat optics. The system includes: a transmitter array configured to emit one or more light beams; a first flat optic configured to receive the light beams from the transmitter array and generate one or more intermediate light beams; a first spacer disposed between the light transmitter array and the first flat optic; a receiver array; a second flat optic configured to receive the intermediate light beams and generate one or more output light beams toward the receiver array; and a second spacer disposed between the second flat optic and the light receiver array. The TX and RX portions of the light coupling system may be used in LiDAR systems as the light emitter (beam steerer) and detector, respectively. The flat optics are configured to provide a wide field of view for the LiDAR.

Abstract: A base station performs joint channel estimation for a set of physical uplink shared channels (PUSCHs) with bundled DMRS from a user equipment (UE). The UE receives an indication to transmit the set of PUSCHs, each PUSCH of the set of PUSCHs comprising a corresponding DMRS from the base station. The base station transmits, and the UE receives, a sounding reference signal resource indicator for each PUSCH of the set of PUSCHs. The UE transmits the PUSCHs based on a same sounding reference single resource, the SRI for a first PUSCH of the set of PUSCHs indicating the same SRS resource.

Abstract: A device includes a memory array, bit line pairs, word lines, a modulation circuit and a control signal generator. The memory array has bit cells arranged in rows and columns. Each bit line pair is connected to a respective column of bit cells. Each word line is connected to a respective row of bit cells. The modulation circuit is coupled with at least one bit line pair. The control signal generator is coupled with the modulation circuit. The control signal generator includes a tracking wiring with a tracking length positively correlated with a depth distance of the word lines. The control signal generator is configured to produce a control signal, switching to a first voltage level for a first time duration in reference with the tracking length, for controlling the modulation circuit. A method of controlling aforesaid device is also disclosed.

Abstract: A lamp and epitaxial processing apparatus are described herein. In one example, the lamp includes a bulb, a filament, and a plurality of filament supports disposed in spaced-apart relation to the filament, each of the filament supports having a hook support and a hook. The hook includes a connector configured to fasten the hook to the hook support, a first vertical portion extending from the connector toward the filament, and a rounded portion extending from an end of the first vertical portion distal from the connector and configured to wrap around the filament. A second vertical portion extends from an end of the rounded portion distal from the first vertical portion and the second vertical portion has a length between 60% and 100% of the length of the first vertical portion.

Abstract: A lithography method in semiconductor fabrication is provided. The method includes generating a plurality of first drops of a target material through a first nozzle group selected from a plurality of nozzles to form a first elongated droplet; generating a first laser pulse to convert the first elongated droplet into plasma that generates a first extreme ultraviolet (EUV) radiation; reflecting the first EUV radiation by a collector mirror having an optical axis; generating a plurality of second drops of the target material through a second nozzle group selected from the plurality of nozzles to form a second elongated droplet, the second elongated droplet being oblique with the optical axis of the collector mirror at a different angle than the first elongated droplet.

Abstract: A method of determining an operational status of a semiconductor manufacturing assembly uses internal vibrations of an in-situ assembly to detect defects. The method may include initiating a first test vibration in an internal structure of the semiconductor manufacturing assembly while the semiconductor manufacturing assembly is in-situ in a semiconductor processing chamber, receiving a first vibration signal caused by the first test vibration, transforming the first vibration signal into a first frequency domain representation of the first vibration signal, determining the operational status of the semiconductor manufacturing assembly based on the first frequency domain representation, and performing a corrective action for the semiconductor manufacturing assembly in response to the operational status.

Abstract: A method of fabricating an integrated circuit includes placing a first set of conductive feature patterns on a first level, placing a second set of conductive feature patterns on a second level, placing a first set of via patterns between the second set of conductive feature patterns and the first set of conductive feature patterns, placing a third set of conductive feature patterns on a third level different from the first level and the second level, placing a second set of via patterns between the third set of conductive feature patterns and the second set of conductive feature patterns, and manufacturing the integrated circuit based on at least one of the above patterns of the integrated circuit.

Abstract: A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a layer stack over a substrate, where the layer stack includes alternating layers of a first dielectric material and a word line (WL) material; forming first trenches extending vertically through the layer stack; filling the first trenches, where filling the first trenches includes forming, in the first trenches, a ferroelectric material, a channel material over the ferroelectric material, and a second dielectric material over the channel material; after filling the first trenches, forming second trenches extending vertically through the layer stack, the second trenches being interleaved with the first trenches; and filling the second trenches, where filling the second trenches includes forming, in the second trenches, the ferroelectric material, the channel material over the ferroelectric material, and the second dielectric material over the channel material.

Abstract: The invention provides a battery module with cooling cartridge and battery system thereof. The cooling cartridge is utilized to be disposed between the battery units stacked in a single axis. The supporting portion of the cooling cartridge is directly contacted in a large area to the current collecting sheet of the battery unit. And the wing portions, extended from the two sides of the supporting portion, are directly contacted to the inner sidewalls of the metal housing. Therefore, a large-area heat dissipating path for the battery cell is provided, and the performance and stability of the battery cell are greatly improved.

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.

Abstract: Provided are a method and apparatus for user's food taste intelligence-based personalized recommendations, wherein the method includes collecting evaluation information including an evaluation of each of a plurality of foods, calculating association scores of the foods on the basis of the evaluation information, and ontology-based information previously possessed for the foods, and recommending one or more foods on the basis of first behavioral information of a user and the association scores.

Abstract: A semiconductor device includes a single-layered dielectric layer, a conductive line, a conductive via and a conductive pad. The conductive line and the conductive via are disposed in the single-layered dielectric layer. The conductive pad is extended into the single-layered dielectric layer to electrically connected to the conductive line.

Abstract: A semiconductor processing method includes: selecting a target state of a reticle based on a given data set, wherein the given data set comprises temperature profiles of the reticle correlated to a target overlay performance, and the target state is a state in which a deformation of the reticle is substantially unchanged; regulating the reticle to reach the target state; and performing an exposure process on a target workpiece by using the reticle.

Abstract: Methods, systems, and devices for wireless communication are described, including techniques for utilizing implicit or explicit signaling to indicate a cancellation of demodulation reference signal (DMRS) bundling. A first user equipment (UE) may perform DMRS bundling across physical sidelink channels transmitted to a second UE to enable the second UE to perform joint channel estimation. In some examples, based on a detected change, either at the first UE or the second UE, the first UE may signal to the second UE that the DMRS bundling is canceled. In some examples, the detected change may be a resource allocation change, a physical channel configuration change, a change in a quasi-colocation (QCL) relationship at the first UE, or a change in a transmission configuration indicator (TCI) state at the first UE. Additionally or alternatively, the first UE or the second UE may request the cancellation based on detected changes.

Abstract: Methods, systems, and devices for wireless communications are described in which a user equipment (UE) may be configured with periodic uplink grants that provide a number of repetitions and a redundancy version (RV) sequence for the repetitions. Prior to the start of an uplink grant period, the UE may determine a set of slots that are available for uplink transmissions in the uplink grant period. Based on the set of slots, the UE may determine a corresponding RV for repetitions of the uplink communication associated with each slot. The slots with uplink transmissions within the uplink grant period may be non-contiguous. Repetitions of an uplink communication may be configured to be transmitted across multiple uplink grant periods, which may be triggered based on a threshold value associated with the repetitions.

Abstract: A cooling system includes a tank, a heat exchanger, a separation tank, a first tube, a second tube, a third tube, a gas storage device, a fourth tube, a first valve, a second valve and a third valve. A heating element is immersed in a dielectric liquid in the tank. The heat exchanger condenses dielectric vapor of the dielectric liquid. The separation tank is used for a separation operation. The first tube is connected to the tank and the heat exchanger. The second tube is connected to the heat exchanger and the separation tank. The third tube is connected to the separation tank and the tank. The gas storage device stores the dielectric vapor. The fourth tube is connected to the gas storage device and the separation tank.

Abstract: A method of forming a semiconductor structure is provided, and includes trimming a first substrate to form a recess on a sidewall of the first substrate. A conductive structure is formed in the first substrate. The method includes bonding the first substrate to a carrier. The method includes thinning down the first substrate. The method also includes forming a dielectric material in the recess and over a top surface of the thinned first substrate. The method further includes performing a planarization process to remove the dielectric material and expose the conductive structure over the top surface. In addition, the method includes removing the carrier from the first substrate.

Abstract: A bimetallic faceplate for substrate processing is provided including a plate having a plurality of gas distribution holes and formed of a first metal having a first coefficient of thermal expansion, the plate having at least one groove around a center of the plate and spaced from the center of the plate; and a metallic element disposed in the at least one groove and fixed to the plate in the at least one groove, the metallic element having a second coefficient of thermal expansion different from the first coefficient of thermal expansion, the metallic element being symmetrically arranged on or in the plate. A chamber for substrate processing is provided that includes a bimetallic faceplate. Also, a method of making a bimetallic faceplate is provided.