Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a redistribution layer (RDL) module, a first semiconductor module, an interconnection module, a second semiconductor module and a molding material. The first semiconductor module is disposed on the RDL module. The interconnection module is disposed on the RDL module. The second semiconductor module is disposed on the interconnection module. The molding material covers the RDL module and surrounds the first semiconductor module and the second semiconductor module. A top surface of the first semiconductor module and a top surface of the second semiconductor module are exposed by the molding material.

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.

Abstract: A cooling system includes a tank, a heat exchanger, a separation tank, a first tube, a second tube, a third tube, a gas storage device, a fourth tube, a first valve, a second valve and a third valve. A heating element is immersed in a dielectric liquid in the tank. The heat exchanger condenses dielectric vapor of the dielectric liquid. The separation tank is used for a separation operation. The first tube is connected to the tank and the heat exchanger. The second tube is connected to the heat exchanger and the separation tank. The third tube is connected to the separation tank and the tank. The gas storage device stores the dielectric vapor. The fourth tube is connected to the gas storage device and the separation tank.

Abstract: A cooling system of server includes a tank and a pressure control device. The tank is configured to accommodate a dielectric fluid. The pressure control device is configured to regulate the pressure of the tank. The pressure control device includes a condenser, a dehumidifier, a gas storage chamber, and a valve. The condenser is connected to the tank. The dehumidifier is connected to the condenser. The gas storage chamber is connected to the dehumidifier. The valve is connected between the dehumidifier and the gas storage chamber. The valve is configured to communicate and not to communicate the dehumidifier and the gas storage chamber.

Abstract: A condenser includes a casing and pipes. The casing includes an inlet chamber, an outlet chamber, a first inlet, a first outlet, an accommodation space, a second inlet, and a second outlet. The first inlet and the first outlet are respectively in fluid communication with the inlet chamber and the outlet chamber. The accommodation space accommodates a coolant, and the second inlet and the second outlet are in fluid communication with the accommodation space not in fluid communication with the inlet chamber and the outlet chamber. The pipes are in the accommodation space and connect the inlet chamber with the outlet chamber, and a working fluid flows from the inlet chamber to the outlet chamber via the pipes. The first inlet is located closer to the second outlet than the first outlet, and the first outlet is located closer to the second inlet than the first inlet.

Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.

Abstract: A liquid level controlling apparatus includes a plurality of main sinks, a storage sink, a pump and a connection tube. One of the plurality of main sinks includes a transmission port and a first liquid level detector. The storage sink includes a delivery port and a second liquid level detector. The pump includes an outlet and an inlet. The connection tube includes an rehydration tube and an drain tube. The rehydration tube has a first rehydration section and a second rehydration section. The first rehydration section is connected between the delivery port and the inlet. The second rehydration section is connected between the outlet and the transmission port. The drain tube has a first drain section and a second drain section. The first drain section is connected between the transmission port and the inlet. The second drain section is connected between the outlet and the delivery port.

Abstract: A liquid level controlling system includes a main sink, a storage sink and a connection tube. The main sink includes a transmission port and a first liquid level detector. The transmission port is formed on a bottom of the main sink. The first liquid level detector is disposed on a top of the main sink. The storage sink includes a liquid outlet, a liquid inlet and a second liquid level detector. The connection tube is disposed between the main sink and the storage sink. The connection tube includes an rehydration tube and an drain tube. Two ends of the rehydration tube are respectively connected to the transmission port and the liquid outlet. Two ends of the drain tube are respectively connected to the transmission port and the liquid inlet.

Abstract: The present disclosure is directed to a semiconductor device. The semiconductor device includes a substrate, an insulating layer disposed on the substrate, a first conductive feature disposed in the insulating layer, and a capacitor structure disposed on the insulating layer. The capacitor structure includes a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, and a third electrode sequentially stacked. The semiconductor device also includes a first via connected to the first electrode and the third electrode, a second via connected to the second electrode, and a third via connected to the first conductive feature. A part of the first via is disposed in the insulating layer. A portion of the first conductive feature is directly under the capacitor structure.

Abstract: A micro light emitting diode structure including an epitaxial structure, a first insulating layer and a second insulating layer is provided. The epitaxial structure includes a first type semiconductor layer, a light emitting layer and a second type semiconductor layer. The first type semiconductor layer, the light emitting layer and a first portion of the second type semiconductor layer form a mesa. A second portion of the second type semiconductor layer is recessed relative the mesa to form a mesa surface. The first insulating layer covers from a top surface of the mesa to the mesa surface along a first side surface of the mesa, and exposes the second side surface. The second insulating layer directly covers a second side surface of the second portion, wherein a thickness ratio of the first insulating layer to the second insulating layer is between 10 and 50.

Abstract: The disclosed subject matter relates to resist compositions that include the following components: Component a) a blend of two Novolak polymers having structures (I) and (II); component b) a diazo-naphthoquinone sulfonate (DNQ-PAC) component which is a single material or a mixture of materials having general formula having structure (III) or having general formula (III-1); is a dissolution enhancer component comprising a polyphenolic compound which is a single compound or a mixture of at least two compounds selected from the group consisting of an oligomeric fractionated Novolak, a compounds having general structure (VI) and a compound having general structure (VII), wherein Rde1, Rde2, Rde3, Rde4 and Rde5 are individually selected from a C-1 to C-4 alkyl; component d) a surfactant; and component e) an organic spin casting solvent, and an optional component f) a heterocyclic thiol.

Abstract: The disclosed subject matter relates to resist compositions comprising a phenolic resin component, a photoactive 2,1,5-diazonaphthoquinonesulfonate component (PAC), a solvent component that do not include or require the use of an added photo acid generator (PAG). The PAC is a free PAC, a coupled PAC (PACb) or a combination thereof that includes a substituted or unsubstituted 2,1,5-DNQ material or compound onto which a substituted or unsubstituted 2,1,5-DNQ material is appended that, when UV exposed, do not form sulfonic acid. The phenolic resin component is a Novolak derivative in which some or all of the free hydroxy groups are protected with an acid cleavable acetal moiety which can include a PACb moiety. The disclosed subject matter also relates to the methods of using the present compositions in either in thick for thin film photoresist device manufacturing methodologies.

Abstract: The present invention relates to resist compositions comprising a polymer component, a photoacid generator component (PAG), a photoactive diazonaphthoquinone component (PAC), a base component, a solvent component, and optionally, a heterocyclic thiol component. The polymer component is a Novolak derivative, comprising Novolak repeat units with free phenolic hydroxy moieties, and Novolak repeat units comprising phenolic hydroxy moieties protected with an acid cleavable acetal moiety.

Abstract: Compounds of formula (I) and polymers comprising at least a structure of formula (II), wherein T1 or T2 are independently of each other a group of Formula (III), Formula (iv) Qa, Qb, Qc, Qd, Qe or Qf are independently of each other O, S or NR1.

Abstract: Compounds of formula (I) and polymers comprising at least a structure of formula (II), wherein T1 or T2 are independently of each other a group of Formula (III), Formula (iv) Qa, Qb, Qc, Qd, Qe or Qf are independently of each other O, S or NR1.