Patents by Inventor Hung-Yi Chung
Hung-Yi Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240144467Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.Type: ApplicationFiled: January 8, 2024Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
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Patent number: 11900586Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.Type: GrantFiled: December 15, 2020Date of Patent: February 13, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
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Publication number: 20230411223Abstract: A method of qualifying semiconductor wafer processing includes: illuminating a semiconductor wafer simultaneously with source light having wavelengths in a plurality of wavebands, including at least a first waveband and a second waveband, the second waveband being different from the first waveband; separating light reflected from the semiconductor wafer as a result of said illuminating, the separating dividing the reflected light according to waveband; generating a first image of the semiconductor wafer based on reflected light separated into the first waveband; and, generating a second image of the semiconductor wafer base on reflected light separated into the second waveband.Type: ApplicationFiled: May 27, 2022Publication date: December 21, 2023Inventors: Shih-Chang Wang, Hsiu-Hui Huang, Hung-Yi Chung, Chien-Huei Chen, Xiaomeng Chen
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Patent number: 11231376Abstract: A method for semiconductor wafer inspection is provided. The method includes the following operations. The semiconductor wafer is scanned to acquire a scanned map, wherein the semiconductor wafer is patterned according to a design map having a programmed defect. The design map and the scanned map are transformed to a transformed inspection map according to the location of the programmed defect on the design map and the location of the programmed defect on the scanned map. The system of semiconductor wafer inspection is also provided.Type: GrantFiled: April 15, 2020Date of Patent: January 25, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chien-Huei Chen, Hung-Yi Chung, Xiaomeng Chen
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Publication number: 20210118125Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.Type: ApplicationFiled: December 15, 2020Publication date: April 22, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
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Publication number: 20210063319Abstract: A method for semiconductor wafer inspection is provided. The method includes the following operations. The semiconductor wafer is scanned to acquire a scanned map, wherein the semiconductor wafer is patterned according to a design map having a programmed defect. The design map and the scanned map are transformed to a transformed inspection map according to the location of the programmed defect on the design map and the location of the programmed defect on the scanned map. The system of semiconductor wafer inspection is also provided.Type: ApplicationFiled: April 15, 2020Publication date: March 4, 2021Inventors: CHIEN-HUEI CHEN, HUNG-YI CHUNG, XIAOMENG CHEN
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Patent number: 10872406Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.Type: GrantFiled: August 29, 2018Date of Patent: December 22, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
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Patent number: 10809635Abstract: A defect inspection method and a defect inspection system are provided. In the method, a plurality of candidate defect images are retrieved from inspection images obtained by at least one optical inspection tool performing hot scans on at least one wafer and a plurality of attributes are extracted from the inspection images. A random forest classifier including a plurality of decision trees for classifying the candidate defect images is created, wherein the decision trees are built with different subset of the attributes and the candidate defect images. A plurality of candidate defect images are retrieved from the optical inspection tool in runtime and applied to the decision trees, and classified into nuisance images and real defect images according to votes of the decision trees in which the nuisance images are filtered out. The real defect images with the votes over a confidence value are sampled for microscopic review.Type: GrantFiled: March 29, 2018Date of Patent: October 20, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Huei Chen, Hung-Yi Chung, Chao-Ting Hong, Cheng-Kuang Lee, Xiaomeng Chen, Teng-Cheng Hsu
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Publication number: 20190318471Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.Type: ApplicationFiled: August 29, 2018Publication date: October 17, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
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Publication number: 20190155164Abstract: A defect inspection method and a defect inspection system are provided. In the method, a plurality of candidate defect images are retrieved from inspection images obtained by at least one optical inspection tool performing hot scans on at least one wafer and a plurality of attributes are extracted from the inspection images. A random forest classifier including a plurality of decision trees for classifying the candidate defect images is created, wherein the decision trees are built with different subset of the attributes and the candidate defect images. A plurality of candidate defect images are retrieved from the optical inspection tool in runtime and applied to the decision trees, and classified into nuisance images and real defect images according to votes of the decision trees in which the nuisance images are filtered out. The real defect images with the votes over a confidence value are sampled for microscopic review.Type: ApplicationFiled: March 29, 2018Publication date: May 23, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Huei Chen, Hung-Yi Chung, Chao-Ting Hong, Cheng-Kuang Lee, Xiaomeng Chen, Teng-Cheng Hsu
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Patent number: 8482128Abstract: A flash memory storage apparatus is provided. The flash memory storage apparatus includes a substrate, a control and storage circuit unit, a ground lead, at least a signal lead, and a power lead. The control and storage circuit unit, the power lead, the signal lead, and the ground lead are disposed on the substrate, in which the power lead, the signal lead, and the ground lead respectively electrically connect to the control and storage circuit unit. Moreover, the flash memory storage apparatus further includes an extra ground lead electrically connected to the ground lead or a protrusion on the substrate, such that the ground lead first electrically connects to a host when the flash memory storage apparatus is plugged into the host.Type: GrantFiled: May 24, 2012Date of Patent: July 9, 2013Assignee: Phison Electronics Corp.Inventors: Yu-Fong Lin, Hung-Yi Chung, Yu-Tong Lin, Yun-Chieh Chen
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Publication number: 20120230102Abstract: A flash memory storage apparatus is provided. The flash memory storage apparatus includes a substrate, a control and storage circuit unit, a ground lead, at least a signal lead, and a power lead. The control and storage circuit unit, the power lead, the signal lead, and the ground lead are disposed on the substrate, in which the power lead, the signal lead, and the ground lead respectively electrically connect to the control and storage circuit unit. Moreover, the flash memory storage apparatus further includes an extra ground lead electrically connected to the ground lead or a protrusion on the substrate, such that the ground lead first electrically connects to a host when the flash memory storage apparatus is plugged into the host.Type: ApplicationFiled: May 24, 2012Publication date: September 13, 2012Applicant: PHISON ELECTRONICS CORP.Inventors: Yu-Fong Lin, Hung-Yi Chung, Yu-Tong Lin, Yun-Chieh Chen
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Patent number: 8222743Abstract: A flash memory storage apparatus is provided. The flash memory storage apparatus includes a substrate, a control and storage circuit unit, a ground lead, at least a signal lead, and a power lead. The control and storage circuit unit, the power lead, the signal lead, and the ground lead are disposed on the substrate, in which the power lead, the signal lead, and the ground lead respectively electrically connect to the control and storage circuit unit. Moreover, the flash memory storage apparatus further includes an extra ground lead electrically connected to the ground lead or a protrusion on the substrate, such that the ground lead first electrically connects to a host when the flash memory storage apparatus is plugged into the host.Type: GrantFiled: May 27, 2009Date of Patent: July 17, 2012Assignee: Phison Electronics Corp.Inventors: Yu-Fong Lin, Hung-Yi Chung, Yu-Tong Lin, Yun-Chieh Chen
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Patent number: 8120903Abstract: A storage apparatus including a circuit board, a first flash memory, a first golden finger, a control unit, and a supporting component is provided. The circuit board has a first surface and a second surface. The first flash memory is disposed on the circuit board. The first golden finger and the control unit are disposed on an end of the circuit board, in which the first golden finger is disposed on the first surface, and the control unit is disposed on the second surface, and the control unit is substantially on the backside of the first golden finger. The control unit is electrically connected with the first memory and the first golden finger. The supporting component is used for supporting the circuit board.Type: GrantFiled: December 29, 2008Date of Patent: February 21, 2012Assignee: Phison Electronics Corp.Inventors: Wei-Hung Lin, Chang-Chih Chen, Hung-Yi Chung
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Publication number: 20100252931Abstract: A flash memory storage apparatus is provided. The flash memory storage apparatus includes a substrate, a control and storage circuit unit, a ground lead, at least a signal lead, and a power lead. The control and storage circuit unit, the power lead, the signal lead, and the ground lead are disposed on the substrate, in which the power lead, the signal lead, and the ground lead respectively electrically connect to the control and storage circuit unit. Moreover, the flash memory storage apparatus further includes an extra ground lead electrically connected to the ground lead or a protrusion on the substrate, such that the ground lead first electrically connects to a host when the flash memory storage apparatus is plugged into the host.Type: ApplicationFiled: May 27, 2009Publication date: October 7, 2010Applicant: PHISON ELECTRONICS CORP.Inventors: YU-FONG LIN, Hung-Yi Chung, Yu-Tong Lin, Yun-Chieh Chen
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Patent number: 7672122Abstract: A flash memory disk includes a holder, a plug, a housing and a pulling ring. The plug is joined with the holder and exposed out of the holder. The housing has a containing space for accommodating the holder and the plug, wherein two sides opposite to each other respectively have a through sliding groove and the third side of the housing there has an opening. The two arms of the pulling ring have sliding blocks, and the sliding blocks are moveable and matched with the through sliding grooves, wherein the pulling ring is rotated about the axis connecting both the sliding blocks, and when the sliding blocks of the pulling ring is moved, the holder would be located between a first position where the plug is entirely accommodated in the containing space and a second position where the plug is entirely protruded out of the opening.Type: GrantFiled: February 19, 2008Date of Patent: March 2, 2010Assignee: Phison Electronics Corp.Inventors: Wei-Hung Lin, Yu-Ting Tseng, Hung-Yi Chung
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Publication number: 20090122478Abstract: A flash memory disk includes a holder, a plug, a housing and a pulling ring. The plug is joined with the holder and exposed out of the holder. The housing has a containing space for accommodating the holder and the plug, wherein two sides opposite to each other respectively have a through sliding groove and the third side of the housing there has an opening. The two arms of the pulling ring have sliding blocks, and the sliding blocks are moveable and matched with the through sliding grooves, wherein the pulling ring is rotated about the axis connecting both the sliding blocks, and when the sliding blocks of the pulling ring is moved, the holder would be located between a first position where the plug is entirely accommodated in the containing space and a second position where the plug is entirely protruded out of the opening.Type: ApplicationFiled: February 19, 2008Publication date: May 14, 2009Applicant: PHISON ELECTRONICS CORP.Inventors: Wei-Hung Lin, Yu-Ting Tseng, Hung-Yi Chung