Patents by Inventor Hung-Yi Hsieh
Hung-Yi Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11953740Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.Type: GrantFiled: May 14, 2021Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
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Patent number: 11947173Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.Type: GrantFiled: May 5, 2023Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
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Patent number: 11943643Abstract: An access point (AP) and a station (STA) communicate with each other, with the AP indicating to the STA either or both of a preamble detection (PD) channel and a signaling (SIG) content channel and with the STA being initially monitoring a primary frequency segment of a plurality of frequency segments in an operating bandwidth of the AP. A downlink (DL) or triggered uplink (UL) communication is performed between the AP and the STA during a transmission opportunity (TXOP) such that: (i) during the TXOP, the STA monitors a preamble on the PD channel and decodes a SIG content on the SIG content channel; and (ii) after an end of the TXOP, the STA switches to the primary frequency segment.Type: GrantFiled: July 21, 2021Date of Patent: March 26, 2024Assignee: MediaTek Singapore Pte. Ltd.Inventors: Kai Ying Lu, Yongho Seok, Hung-Tao Hsieh, Cheng-Yi Chang, James Chih-Shi Yee, Jianhan Liu, Po-Yuen Cheng
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Patent number: 11935841Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a device package and a shielding layer. The device package includes an electronic device unit and has a first surface, a second surface opposite to the first surface, and a third surface connecting the first surface to the second surface. The shielding layer is disposed on the first surface and the second surface of the device package. A common edge of the second surface and the third surface includes a first portion exposed from the shielding layer by a first length, and a common edge of the first surface and the third surface includes a second portion exposed from the shielding layer by a second length that is different from the first length.Type: GrantFiled: November 18, 2022Date of Patent: March 19, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Cheng-Yuan Kung, Hung-Yi Lin, Meng-Wei Hsieh, Yu-Pin Tsai
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Publication number: 20240080024Abstract: A driving method for a multiple frequency coupling generator is provided. The method includes: in normal operations, interpreting an input digital control signal transmitted from a digital signal processor into an interpreted digital control signal; interpreting the interpreted digital control signal into a plurality of magnetic coupling signals by a magnetic coupling switch circuit; performing signal recovery and differential delay on the magnetic coupling signals by an interlocking circuit for reducing time difference and signal loss of the magnetic coupling signals; and when the interlocking circuit determines that the magnetic coupling signals have substantially no time difference and no signal loss, transforming the magnetic coupling signals into a first driving signal and a second driving signal by a switch circuit, a driver circuit and an output pad group to drive a backend driving loop.Type: ApplicationFiled: March 30, 2023Publication date: March 7, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chih-Chung CHIU, Hung-Yi TENG, Chi-Chung LIAO, Shou-Chung HSIEH, Ke-Horng CHEN, Yan-Fu JHOU
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Publication number: 20240069277Abstract: A semiconductor package includes a first die stack structure and a second die stack structure, an insulating encapsulation, a redistribution structure, at least one prism structure and at least one reflector. The first die stack structure and the second die stack structure are laterally spaced apart from each other along a first direction, and each of the first die stack structure and the second die stack structure comprises an electronic die; and a photonic die electronically communicating with the electronic die. The insulating encapsulation laterally encapsulates the first die stack structure and the second die stack structure. The redistribution structure is disposed on the first die stack structure, the second die stack structure and the insulating encapsulation, and electrically connected to the first die stack structure and the second die stack structure. The at least one prism structure is disposed within the redistribution structure and optically coupled to the photonic die.Type: ApplicationFiled: August 29, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Yi Kuo, Chen-Hua Yu, Cheng-Chieh Hsieh, Che-Hsiang Hsu, Chung-Ming Weng, Tsung-Yuan Yu
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Publication number: 20230400871Abstract: A low-dropout (LDO) regulator having an analog low-dropout (ALDO) regulating circuit assisted by a digital low-dropout (DLDO) regulating circuit is shown. The DLDO regulating circuit is coupled to the ALDO regulating circuit, and senses operating information that shows if the ALDO regulating circuit is within its operating region. The DLDO regulating circuit assists the ALDO regulating circuit based on the operating information of the ALDO regulating circuit instead of an output voltage at the output terminal of the LDO regulator.Type: ApplicationFiled: April 24, 2023Publication date: December 14, 2023Inventor: Hung-Yi HSIEH
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Patent number: 11265010Abstract: An incremental analog-to-digital converter (ADC) with high accuracy. The incremental ADC has a delta-sigma modulator, performing delta-sigma modulation on an analog input signal to output a quantized signal, and a digital filter, receiving the quantized signal to generate a digital representation of the analog input signal. A loop filter of the delta-sigma modulator has a preset circuit. In the preset circuit, the output terminal of the loop filter is preset rather than being reset during the reset phase of the incremental ADC.Type: GrantFiled: April 1, 2020Date of Patent: March 1, 2022Assignee: MEDIATEK INC.Inventors: Yun-Shiang Shu, Su-Hao Wu, Hung-Yi Hsieh, Albert Yen-Chih Chiou
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Patent number: 11128496Abstract: A transmitter with low power and high accuracy equalization is shown. The transmitter includes a transmitter driver and a driver bias circuit. The transmitter driver receives data, and generates a positive differential output and a negative differential output to be transmitted by the transmitter. The driver bias circuit is coupled to the transmitter driver to bias the transmitter driver, wherein the driver bias circuit is configured to boost the bias level of the transmitter driver in response to transitions of the data.Type: GrantFiled: July 23, 2020Date of Patent: September 21, 2021Assignee: MEDIATEK INC.Inventor: Hung-Yi Hsieh
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Patent number: 11121720Abstract: The present invention provides an ADC including a first switched capacitor array, a second switched capacitor array, a third switched capacitor array, an integrator and a quantizer. The first switched capacitor array is configured to sample the input signal to generate a first sampled signal. The second switched capacitor array is configured to sample the input signal to generate a second sampled signal and generate a first quantization error. The third switched capacitor array is configured to sample the input signal to generate a third sampled signal and generate a second quantization error. The integrator is configured to receive the first quantization error and the second quantization error in a time-interleaving manner, and integrate the first/second quantization error to generate an integrated quantization error. The quantizer is configured to quantize the first sampled signal by using the integrated quantization error as a reference voltage to generate a digital output signal.Type: GrantFiled: July 20, 2020Date of Patent: September 14, 2021Assignee: MEDIATEK INC.Inventors: Chan-Hsiang Weng, Hung-Yi Hsieh, Tzu-An Wei, Ting-Yang Wang
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Publication number: 20210152399Abstract: A transmitter with low power and high accuracy equalization is shown. The transmitter includes a transmitter driver and a driver bias circuit. The transmitter driver receives data, and generates a positive differential output and a negative differential output to be transmitted by the transmitter. The driver bias circuit is coupled to the transmitter driver to bias the transmitter driver, wherein the driver bias circuit is configured to boost the bias level of the transmitter driver in response to transitions of the data.Type: ApplicationFiled: July 23, 2020Publication date: May 20, 2021Inventor: Hung-Yi HSIEH
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Patent number: 10944418Abstract: The present invention provides an ADC for receiving at least an input signal to generate a digital output signal, wherein the ADC includes an input terminal and a plurality of output terminals, the input terminal is arranged to receive the input signal, and each of the output terminals is configured to output one bit of the digital output signal. The ADC is controlled to operate in a normal mode or a low power mode, and when the ADC operates in the normal mode, all of the output terminals are enabled to output the bits to form the digital output signal; and when the ADC operates in the low power mode, only a portion of the output terminals are enabled to output the bits to form the digital output signal.Type: GrantFiled: November 12, 2018Date of Patent: March 9, 2021Assignee: MediaTek Inc.Inventors: Ting-Yang Wang, Hung-Yi Hsieh, Tzu-An Wei, Tien-Yu Lo
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Publication number: 20210044301Abstract: The present invention provides an ADC including a first switched capacitor array, a second switched capacitor array, a third switched capacitor array, an integrator and a quantizer. The first switched capacitor array is configured to sample the input signal to generate a first sampled signal. The second switched capacitor array is configured to sample the input signal to generate a second sampled signal and generate a first quantization error. The third switched capacitor array is configured to sample the input signal to generate a third sampled signal and generate a second quantization error. The integrator is configured to receive the first quantization error and the second quantization error in a time-interleaving manner, and integrate the first/second quantization error to generate an integrated quantization error. The quantizer is configured to quantize the first sampled signal by using the integrated quantization error as a reference voltage to generate a digital output signal.Type: ApplicationFiled: July 20, 2020Publication date: February 11, 2021Inventors: Chan-Hsiang Weng, Hung-Yi Hsieh, Tzu-An Wei, Ting-Yang Wang
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Patent number: 10833631Abstract: The present invention provides a continuous time circuit including an amplifier and a RC calibration circuit. In the operations of the continuous time circuit, the amplifier is configured to amplify an input signal to generate an output signal, and the RC calibration circuit is configured to adjust a capacitance of a compensation capacitor of the amplifier according to a RC product measurement result.Type: GrantFiled: November 26, 2018Date of Patent: November 10, 2020Assignee: MEDIATEK INC.Inventors: Hung-Yi Hsieh, Jui-Yuan Tsai
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Publication number: 20200343905Abstract: An incremental analog-to-digital converter (ADC) with high accuracy. The incremental ADC has a delta-sigma modulator, performing delta-sigma modulation on an analog input signal to output a quantized signal, and a digital filter, receiving the quantized signal to generate a digital representation of the analog input signal. A loop filter of the delta-sigma modulator has a preset circuit. In the preset circuit, the output terminal of the loop filter is preset rather than being reset during the reset phase of the incremental ADC.Type: ApplicationFiled: April 1, 2020Publication date: October 29, 2020Inventors: Yun-Shiang SHU, Su-Hao WU, Hung-Yi HSIEH, Albert Yen-Chih CHIOU
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Patent number: 10374626Abstract: The present invention provides a continuous-time delta-sigma modulator comprising two ADCs. One of the ADC is configured to generate MSBs of an output signal of the continuous-time delta-sigma modulator, and the other ADC is configured to generate LSBs of the output signal. In addition, the two ADCs sample an output of a loop filter at different times, but the MSBs and LSBs are feedback to the loop filter simultaneously.Type: GrantFiled: September 18, 2018Date of Patent: August 6, 2019Assignee: MEDIATEK INC.Inventor: Hung-Yi Hsieh
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Publication number: 20190238093Abstract: The present invention provides a continuous time circuit including an amplifier and a RC calibration circuit. In the operations of the continuous time circuit, the amplifier is configured to amplify an input signal to generate an output signal, and the RC calibration circuit is configured to adjust a capacitance of a compensation capacitor of the amplifier according to a RC product measurement result.Type: ApplicationFiled: November 26, 2018Publication date: August 1, 2019Inventors: Hung-Yi Hsieh, Jui-Yuan Tsai
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Publication number: 20190238151Abstract: The present invention provides an ADC for receiving at least an input signal to generate a digital output signal, wherein the ADC includes an input terminal and a plurality of output terminals, the input terminal is arranged to receive the input signal, and each of the output terminals is configured to output one bit of the digital output signal. The ADC is controlled to operate in a normal mode or a low power mode, and when the ADC operates in the normal mode, all of the output terminals are enabled to output the bits to form the digital output signal; and when the ADC operates in the low power mode, only a portion of the output terminals are enabled to output the bits to form the digital output signal.Type: ApplicationFiled: November 12, 2018Publication date: August 1, 2019Inventors: Ting-Yang Wang, Hung-Yi Hsieh, Tzu-An Wei, Tien-Yu Lo
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Publication number: 20190158111Abstract: The present invention provides a continuous-time delta-sigma modulator comprising two ADCs. One of the ADC is configured to generate MSBs of an output signal of the continuous-time delta-sigma modulator, and the other ADC is configured to generate LSBs of the output signal. In addition, the two ADCs sample an output of a loop filter at different times, but the MSBs and LSBs are feedback to the loop filter simultaneously.Type: ApplicationFiled: September 18, 2018Publication date: May 23, 2019Inventor: Hung-Yi Hsieh
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Patent number: 9985645Abstract: A delta-sigma modulator includes a receiving circuit, a loop filter, a quantizer, a dynamic element matching circuit and a digital to analog converter. The receiving circuit is arranged for receiving a feedback signal and an input signal to generate a summation signal. The loop filter is arranged for receiving the summation signal to generate a filtered summation signal. The quantizer is arranged for generating a digital output signal according to the filtered summation signal. The dynamic element matching circuit is arranged for receiving the digital output signal to generate a shaped digital output signal for shaping element mismatch. The digital to analog converter is arranged for performing a digital to analog converting operation upon a signal derived from the shaped digital output signal to generate the feedback signal to the receiving circuit, wherein clock signals used by the quantizer and the dynamic element matching circuit have different frequencies.Type: GrantFiled: July 18, 2017Date of Patent: May 29, 2018Assignee: MEDIATEK INC.Inventors: Pao-Cheng Chiu, Hung-Yi Hsieh