Patents by Inventor Hung-Yi Huang

Hung-Yi Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250253823
    Abstract: An on-chip variable termination circuit includes a plurality of first tuning circuits and a plurality of second tuning circuits. Each of the first tuning circuits is coupled between a positive signal node of a differential signal port and a voltage node. The first tuning circuits include at least one amplitude tuning circuit and at least one phase tuning circuit. Each of the second tuning circuits is coupled between a negative signal node of the differential signal port and the voltage node. The second tuning circuits include at least one amplitude tuning circuit and at least one phase tuning circuit.
    Type: Application
    Filed: January 16, 2025
    Publication date: August 7, 2025
    Applicant: MediaTek Inc.
    Inventors: Min-Jui Chiu, Hung-Yi Huang, Wei-Te Lin
  • Publication number: 20250254907
    Abstract: A semiconductor device includes a gate structure on a semiconductor fin, a dielectric layer on the gate structure, and a gate contact extending through the dielectric layer to the gate structure. The gate contact includes a first conductive material on the gate structure, a top surface of the first conductive material extending between sidewalls of the dielectric layer, and a second conductive material on the top surface of the first conductive material.
    Type: Application
    Filed: April 23, 2025
    Publication date: August 7, 2025
    Inventors: Kan-Ju Lin, Chien Chang, Chih-Shiun Chou, TaiMin Chang, Hung-Yi Huang, Chih-Wei Chang, Ming-Hsing Tsai, Lin-Yu Huang
  • Publication number: 20250246551
    Abstract: An interconnect structure and a method of fabricating the interconnect structure are disclosed. The interconnect structure includes an inter-metal dielectric (IMD) structure disposed on a transistor, first and second conductive lines disposed in the IMD structure, and a third conductive line, disposed in the IMD structure. The first conductive line includes a top surface with a first width and a bottom surface with a second width greater than the first width. The third conductive line includes an upper surface with a third width and a lower surface with a fourth width smaller than the third width. Metals of the first and third conductive lines are different from each other.
    Type: Application
    Filed: October 23, 2024
    Publication date: July 31, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chi LO, Chih-Yi CHANG, Hung-Yi HUANG, Wei-Yip LOH
  • Publication number: 20250221034
    Abstract: A semiconductor device includes an oxide diffusion (OD) area; at least one first poly gate, formed above the OD area; and a plurality of second poly gates, formed on both sides of the at least one first poly gate and above the OD area. The plurality of second poly gates are OD edge dummy gates that are used to reduce length of oxide diffusion (LOD) effect, and at least a portion of the plurality of second poly gates are reused to implement at least one delay circuit.
    Type: Application
    Filed: December 27, 2024
    Publication date: July 3, 2025
    Applicant: MEDIATEK INC.
    Inventors: Hung-Yi Huang, Wei-Te Lin, Wei-Hsin Tseng
  • Patent number: 12341013
    Abstract: A method includes receiving a structure having a dielectric layer over a conductive feature, wherein the conductive feature includes a second metal. The method further includes etching a hole through the dielectric layer and exposing the conductive feature and depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature, wherein the first metal entirely fills the hole. The method further includes annealing the structure such that atoms of the second metal are diffused into grain boundaries of the first metal and into interfaces between the first metal and the dielectric layer. After the annealing, the method further includes performing a chemical mechanical planarization (CMP) process to remove at least a portion of the first metal.
    Type: Grant
    Filed: June 27, 2024
    Date of Patent: June 24, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sung-Li Wang, Hung-Yi Huang, Yu-Yun Peng, Mrunal A. Khaderbad, Chia-Hung Chu, Shuen-Shin Liang, Keng-Chu Lin
  • Patent number: 12327788
    Abstract: A method for manufacturing a semiconductor device includes: forming a lower metal contact in a trench of a first dielectric structure, the lower metal contact having a height less than a depth of the trench and being made of a first metal material; forming an upper metal contact to fill the trench and to be in contact with the lower metal contact, the upper metal contact being formed of a second metal material different from the first metal material and having a bottom surface with a dimension the same as a dimension of a top surface of the lower metal contact; forming a second dielectric structure on the first dielectric structure; and forming a via contact penetrating through the second dielectric structure to be electrically connected to the upper metal contact, the via contact being formed of a metal material the same as the second metal material.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: June 10, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shuen-Shin Liang, Chia-Hung Chu, Po-Chin Chang, Tzu-Pei Chen, Ken-Yu Chang, Hung-Yi Huang, Harry Chien, Wei-Yip Loh, Chun-I Tsai, Hong-Mao Lee, Sung-Li Wang, Pinyen Lin
  • Patent number: 12327058
    Abstract: At least two display areas are formed after an action such as folding a foldable screen of a device. The device displays a first display interface comprising a display interface of a first application. The device detects a first operation such as unfolding the screen and in response, displays a second display interface comprising a first display area and a second display area. The device displays the display interface of the first application in the first display area of the second display interface, and displays at least one application icon in the second display area of the second display interface. The device detects a second operation acting on an application icon corresponding to the first target application and in response, displays a third display interface that comprises the first display area and the second display area.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: June 10, 2025
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Qinghao Jin, Hung-yi Huang
  • Publication number: 20250183040
    Abstract: In a semiconductor structure, a first conductive feature is formed in a trench by PVD and a glue layer is then deposited on the first conductive feature in the trench before CVD deposition of a second conductive feature there-over. The first conductive feature acts as a protection layer to keep silicide from being damaged by later deposition of metal or a precursor by CVD. The glue layer extends along the extent of the sidewall to enhance the adhesion of the second conductive features to the surrounding dielectric layer.
    Type: Application
    Filed: February 12, 2025
    Publication date: June 5, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Hsuan LU, Kan-Ju LIN, Lin-Yu HUANG, Sheng-Tsung WANG, Hung-Yi HUANG, Chih-Wei CHANG, Ming-Hsing TSAI, Chih-Hao WANG
  • Patent number: 12255070
    Abstract: In a semiconductor structure, a first conductive feature is formed in a trench by PVD and a glue layer is then deposited on the first conductive feature in the trench before CVD deposition of a second conductive feature there-over. The first conductive feature acts as a protection layer to keep silicide from being damaged by later deposition of metal or a precursor by CVD. The glue layer extends along the extent of the sidewall to enhance the adhesion of the second conductive features to the surrounding dielectric layer.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: March 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Min-Hsuan Lu, Kan-Ju Lin, Lin-Yu Huang, Sheng-Tsung Wang, Hung-Yi Huang, Chih-Wei Chang, Ming-Hsing Tsai, Chih-Hao Wang
  • Publication number: 20250062232
    Abstract: A method includes forming a conductive layer over a first dielectric layer; etching a recess in the conductive layer, wherein the recess exposes a top surface of the first dielectric layer; selectively depositing a capping layer on exposed sidewalls of the conductive layer within the recess; depositing a liner on the capping layer; forming a sacrificial material in the recess; and forming a second dielectric layer on the sacrificial material and on sidewalls of the recess; and after forming the second dielectric layer, performing a thermal process to remove the sacrificial material.
    Type: Application
    Filed: December 5, 2023
    Publication date: February 20, 2025
    Inventors: Ming-Chou Chiang, Chih-Yi Chang, Hung-Yi Huang
  • Patent number: 12199656
    Abstract: A screen protection member includes a protection film and a frame. The protection film includes a bonding surface. The frame is fastened to a peripheral region of the bonding surface by surrounding the peripheral region. The frame has at least one notch group. A single notch group includes two notches that are disposed opposite to each other. The at least one notch group divides the frame into at least two frame parts that are spaced apart from each other.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: January 14, 2025
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jenhui Liao, Hung-Yi Huang
  • Publication number: 20240413211
    Abstract: Device-level interconnects having high thermal stability for stacked device structures are disclosed herein. An exemplary stacked semiconductor structure includes an upper source/drain contact disposed on an upper epitaxial source/drain, a lower source/drain contact disposed on a lower epitaxial source/drain, and a source/drain via connected to the upper source/drain contact and the lower source/drain contact. The source/drain via is disposed on the upper source/drain contact, the source/drain via extends below the upper source/drain contact, and the source/drain via includes ruthenium and aluminum. In some embodiments, the source/drain via includes a ruthenium plug wrapped by an aluminum liner. In some embodiments, the source/drain via includes a ruthenium aluminide plug. In some embodiments, the source/drain via includes a ruthenium plug wrapped by a ruthenium aluminide liner. In some embodiments, the source/drain via extends below a top of the lower epitaxial source/drain.
    Type: Application
    Filed: November 28, 2023
    Publication date: December 12, 2024
    Inventors: Wei-Yip Loh, Liang-Yueh Ou Yang, Hung-Yi Huang, Harry Chien, Chun-Chieh Lin
  • Publication number: 20240404876
    Abstract: Semiconductor devices and methods of manufacturing are provided. In some embodiments the method includes depositing an etch stop layer over a first hard mask material, the first hard mask material over a gate stack, depositing an interlayer dielectric over the etch stop layer, forming a first opening through the interlayer dielectric, the etch stop layer, and the first hard mask material, the first opening exposing a conductive portion of the gate stack, and treating sidewalls of the first opening with a first dopant to form a first treated region within the interlayer dielectric, a second treated region within the etch stop layer, a third treated region within the first hard mask material, and a fourth treated region within the conductive portion, wherein after the treating the fourth treated region has a higher concentration of the first dopant than the first treated region.
    Type: Application
    Filed: July 30, 2024
    Publication date: December 5, 2024
    Inventors: Kan-Ju Lin, Chien Chang, Chih-Shiun Chou, Tai Min Chang, Yi-Ning Tai, Hung-Yi Huang, Chih-Wei Chang, Ming-Hsing Tsai, Lin-Yu Huang
  • Publication number: 20240387288
    Abstract: Techniques described herein enable respective (different) types of metal silicide layers to be formed for p-type source/drain regions and n-type source/drain regions in a selective manner. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective). This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Wei-Yip LOH, Yan-Ming TSAI, Yi-Ning TAI, Raghunath PUTIKAM, Hung-Yi HUANG, Hung-Hsu CHEN, Chih-Wei CHANG
  • Publication number: 20240379423
    Abstract: A barrier layer is formed in a portion of a thickness of sidewalls in a recess prior to formation of an interconnect structure in the recess. The barrier layer is formed in the portion of the thickness of the sidewalls by a plasma-based deposition operation, in which a precursor reacts with a silicon-rich surface to form the barrier layer. The barrier layer is formed in the portion of the thickness of the sidewalls in that the precursor consumes a portion of the silicon-rich surface of the sidewalls as a result of the plasma treatment. This enables the barrier layer to be formed in a manner in which the cross-sectional width reduction in the recess from the barrier layer is minimized while enabling the barrier layer to be used to promote adhesion in the recess.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Chien CHANG, Min-Hsiu HUNG, Yu-Hsiang LIAO, Yu-Shiuan WANG, Tai Min CHANG, Kan-Ju LIN, Chih-Shiun CHOU, Hung-Yi HUANG, Chih-Wei CHANG, Ming-Hsing TSAI
  • Publication number: 20240363339
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.
    Type: Application
    Filed: July 12, 2024
    Publication date: October 31, 2024
    Inventors: Cheng-Wei Chang, Min-Hsiu Hung, Hung-Yi Huang, Chun Chieh Wang, Yu-Ting Lin
  • Publication number: 20240355741
    Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.
    Type: Application
    Filed: July 1, 2024
    Publication date: October 24, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuen-Shin LIANG, Chun-I TSAI, Chih-Wei CHANG, Chun-Hsien HUANG, Hung-Yi HUANG, Keng-Chu LIN, Ken-Yu CHANG, Sung-Li WANG, Chia-Hung CHU, Hsu-Kai CHANG
  • Publication number: 20240347342
    Abstract: A method includes receiving a structure having a dielectric layer over a conductive feature, wherein the conductive feature includes a second metal. The method further includes etching a hole through the dielectric layer and exposing the conductive feature and depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature, wherein the first metal entirely fills the hole. The method further includes annealing the structure such that atoms of the second metal are diffused into grain boundaries of the first metal and into interfaces between the first metal and the dielectric layer. After the annealing, the method further includes performing a chemical mechanical planarization (CMP) process to remove at least a portion of the first metal.
    Type: Application
    Filed: June 27, 2024
    Publication date: October 17, 2024
    Inventors: Sung-Li Wang, Hung-Yi Huang, Yu-Yun Peng, Mrunal A. Khaderbad, Chia-Hung Chu, Shuen-Shin Liang, Keng-Chu Lin
  • Patent number: 12087575
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: September 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Wei Chang, Min-Hsiu Hung, Hung-Yi Huang, Chun Chieh Wang, Yu-Ting Lin
  • Patent number: D1045888
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: October 8, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Lingsong Jin, Hung-Yi Huang, Bin Xie