Abstract: Preparations capable of forming films are disclosed. The preparations include a biocompatible polymer and a purified amphiphilic peptide including a folding group having a plurality of charged amino acid residues and hydrophobic amino acid residues arranged in a substantially alternating pattern and a turn sequence, and at least one functional group available for crosslinking. The purified amphiphilic peptide is crosslinked with the biocompatible polymer to form the film. Kits for producing the film are also disclosed. Methods of producing the film are also disclosed.

Abstract: Methods of introducing a hydrogel into a subject, including administering a thermally stable preparation containing a purified amphiphilic peptide to the subject by injection are disclosed. Methods of treating a subject including administering a thermally stable preparation containing a purified amphiphilic peptide by injection are disclosed. Methods of applying a hydrogel to a subject, including topically administering a thermally stable preparation containing a purified amphiphilic peptide to the subject are disclosed. Methods of treating a subject including topically administering a thermally stable preparation containing a purified amphiphilic peptide are also disclosed. Methods of treating biofilm by topically administering a thermally stable preparation containing a purified amphiphilic peptide are disclosed. Methods of treating biofilm by administering by injection a thermally stable preparation containing a purified amphiphilic peptide are also disclosed.

Abstract: A distributed key generation system and a key generation method are provided. The distributed key generation system includes a plurality of electronic devices and a server device. Each electronic device sends a data fragment. The server device synthesizes the key according to the data fragments. In this way, the key is not generated in advance, which can reduce the risk of key leakage.

Abstract: A computer-implemented method obtains data describing a plurality of synthesis scenarios associated with a very-large-scale integration design (VLSI), wherein each synthesis scenario describes a different combination of tunable design parameters for a macro of the VLSI design, and wherein the VLSI design includes a plurality of macros being tuned. The plurality of macros is ranked based on the data. The ranking produces a macro waiting list that identifies those of the synthesis scenarios that are associated with each of the macros. A subset of the synthesis scenarios is pushed from the macro waiting list to a job submission queue that is separate from the macro waiting list. The job submission queue ranks the subset of synthesis scenarios in an order in which they are to be synthesized by a synthesis tuning system. At least one synthesis scenario is submitted to the synthesis tuning system according to the order.

Abstract: A computer-implemented method obtains data describing a plurality of synthesis scenarios associated with a very-large-scale integration design (VLSI), wherein each synthesis scenario describes a different combination of tunable design parameters for a macro of the VLSI design, and wherein the VLSI design includes a plurality of macros being tuned. The plurality of macros is ranked based on the data. The ranking produces a macro waiting list that identifies those of the synthesis scenarios that are associated with each of the macros. A subset of the synthesis scenarios is pushed from the macro waiting list to a job submission queue that is separate from the macro waiting list. The job submission queue ranks the subset of synthesis scenarios in an order in which they are to be synthesized by a synthesis tuning system. At least one synthesis scenario is submitted to the synthesis tuning system according to the order.

Abstract: A computer-implemented method obtains data describing a plurality of synthesis scenarios associated with a very-large-scale integration design (VLSI), wherein each synthesis scenario describes a different combination of tunable design parameters for a macro of the VLSI design, and wherein the VLSI design includes a plurality of macros being tuned. The plurality of macros is ranked based on the data. The ranking produces a macro waiting list that identifies those of the synthesis scenarios that are associated with each of the macros. A subset of the synthesis scenarios is pushed from the macro waiting list to a job submission queue that is separate from the macro waiting list. The job submission queue ranks the subset of synthesis scenarios in an order in which they are to be synthesized by a synthesis tuning system. At least one synthesis scenario is submitted to the synthesis tuning system according to the order.

Abstract: A method and system are provided for tuning parameters of a synthesis program for a design description. The method includes (a) ranking individual parameter impact by evaluating a design-cost function of each of the parameters. The method further includes (b) creating a set of possible parameter combinations that is ordered by an estimated-cost function. The method additionally includes (c) selecting, from the set of possible parameter combinations, top-k scenarios having best estimated costs to form a potential set, and running at least some of the top-k scenarios in parallel through the synthesis program. The method also includes (d) repeating steps (b)-(c) for one or more iterations until at least one of a maximum iteration limit is reached and an exit criterion is satisfied.

Abstract: A method and system are provided for tuning parameters of a synthesis program for a design description. The method includes (a) ranking individual parameter impact by evaluating a design-cost function of each of the parameters. The method further includes (b) creating a set of possible parameter combinations that is ordered by an estimated-cost function. The method additionally includes (c) selecting, from the set of possible parameter combinations, top-k scenarios having best estimated costs to form a potential set, and running at least some of the top-k scenarios in parallel through the synthesis program. The method also includes (d) repeating steps (b)-(c) for one or more iterations until at least one of a maximum iteration limit is reached and an exit criterion is satisfied.

Abstract: A method and system are provided for tuning parameters of a synthesis program for a design description. The method includes (a) ranking individual parameter impact by evaluating a design-cost function of each of the parameters. The method further includes (b) creating a set of possible parameter combinations that is ordered by an estimated-cost function. The method additionally includes (c) selecting, from the set of possible parameter combinations, top-k scenarios having best estimated costs to form a potential set, and running at least some of the top-k scenarios in parallel through the synthesis program. The method also includes (d) repeating steps (b)-(c) for one or more iterations until at least one of a maximum iteration limit is reached and an exit criterion is satisfied.

Abstract: A method and system are provided for tuning parameters of a synthesis program for a design description. The method includes (a) ranking individual parameter impact by evaluating a design-cost function of each of the parameters. The method further includes (b) creating a set of possible parameter combinations that is ordered by an estimated-cost function. The method additionally includes (c) selecting, from the set of possible parameter combinations, top-k scenarios having best estimated costs to form a potential set, and running at least some of the top-k scenarios in parallel through the synthesis program. The method also includes (d) repeating steps (b)-(c) for one or more iterations until at least one of a maximum iteration limit is reached and an exit criterion is satisfied.

Abstract: A method and system are provided for tuning parameters of a synthesis program for a design description. The method includes (a) ranking individual parameter impact by evaluating a design-cost function of each of the parameters. The method further includes (b) creating a set of possible parameter combinations that is ordered by an estimated-cost function. The method additionally includes (c) selecting, from the set of possible parameter combinations, top-k scenarios having best estimated costs to form a potential set, and running at least some of the top-k scenarios in parallel through the synthesis program. The method also includes (d) repeating steps (b)-(c) for one or more iterations until at least one of a maximum iteration limit is reached and an exit criterion is satisfied.

Abstract: A computer-implemented method obtains data describing a plurality of synthesis scenarios associated with a very-large-scale integration design (VLSI), wherein each synthesis scenario describes a different combination of tunable design parameters for a macro of the VLSI design, and wherein the VLSI design includes a plurality of macros being tuned. The plurality of macros is ranked based on the data. The ranking produces a macro waiting list that identifies those of the synthesis scenarios that are associated with each of the macros. A subset of the synthesis scenarios is pushed from the macro waiting list to a job submission queue that is separate from the macro waiting list. The job submission queue ranks the subset of synthesis scenarios in an order in which they are to be synthesized by a synthesis tuning system. At least one synthesis scenario is submitted to the synthesis tuning system according to the order.

Abstract: A computer-implemented method obtains data describing a plurality of synthesis scenarios associated with a very-large-scale integration design (VLSI), wherein each synthesis scenario describes a different combination of tunable design parameters for a macro of the VLSI design, and wherein the VLSI design includes a plurality of macros being tuned. The plurality of macros is ranked based on the data. The ranking produces a macro waiting list that identifies those of the synthesis scenarios that are associated with each of the macros. A subset of the synthesis scenarios is pushed from the macro waiting list to a job submission queue that is separate from the macro waiting list. The job submission queue ranks the subset of synthesis scenarios in an order in which they are to be synthesized by a synthesis tuning system. At least one synthesis scenario is submitted to the synthesis tuning system according to the order.

Abstract: A computer-implemented method obtains data describing a plurality of synthesis scenarios associated with a very-large-scale integration design (VLSI), wherein each synthesis scenario describes a different combination of tunable design parameters for a macro of the VLSI design, and wherein the VLSI design includes a plurality of macros being tuned. The plurality of macros is ranked based on the data. The ranking produces a macro waiting list that identifies those of the synthesis scenarios that are associated with each of the macros. A subset of the synthesis scenarios is pushed from the macro waiting list to a job submission queue that is separate from the macro waiting list. The job submission queue ranks the subset of synthesis scenarios in an order in which they are to be synthesized by a synthesis tuning system. At least one synthesis scenario is submitted to the synthesis tuning system according to the order.

Abstract: A method and system are provided for tuning parameters of a synthesis program for a design description. The method includes (a) ranking individual parameter impact by evaluating a design-cost function of each of the parameters. The method further includes (b) creating a set of possible parameter combinations that is ordered by an estimated-cost function. The method additionally includes (c) selecting, from the set of possible parameter combinations, top-k scenarios having best estimated costs to form a potential set, and running at least some of the top-k scenarios in parallel through the synthesis program. The method also includes (d) repeating steps (b)-(c) for one or more iterations until at least one of a maximum iteration limit is reached and an exit criterion is satisfied.

Abstract: A method and system are provided for tuning parameters of a synthesis program for a design description. The method includes (a) ranking individual parameter impact by evaluating a design-cost function of each of the parameters. The method further includes (b) creating a set of possible parameter combinations that is ordered by an estimated-cost function. The method additionally includes (c) selecting, from the set of possible parameter combinations, top-k scenarios having best estimated costs to form a potential set, and running at least some of the top-k scenarios in parallel through the synthesis program. The method also includes (d) repeating steps (b)-(c) for one or more iterations until at least one of a maximum iteration limit is reached and an exit criterion is satisfied.

Abstract: A method and system are provided for tuning parameters of a synthesis program for a design description. The method includes (a) ranking individual parameter impact by evaluating a design-cost function of each of the parameters. The method further includes (b) creating a set of possible parameter combinations that is ordered by an estimated-cost function. The method additionally includes (c) selecting, from the set of possible parameter combinations, top-k scenarios having best estimated costs to form a potential set, and running at least some of the top-k scenarios in parallel through the synthesis program. The method also includes (d) repeating steps (b)-(c) for one or more iterations until at least one of a maximum iteration limit is reached and an exit criterion is satisfied.

Abstract: A method of inserting dummy metal and dummy via in an integrated circuit design includes inserting, by a computer, dummy metals using a place and route tool, wherein the place and route tool has timing-awareness to improve a timing performance of the integrated circuit design, and the dummy metals have a length less than or equal to a predetermined maximum length. The method further includes inserting, by the computer, dummy vias using a design-rule-checking utility separately from the inserting of the dummy metals.

Abstract: A method of inserting dummy metal and dummy via in an integrated circuit design includes inserting, by a computer, dummy metals using a place and route tool, wherein the place and route tool has timing-awareness to improve a timing performance of the integrated circuit design, and the dummy metals have a length less than or equal to a predetermined maximum length. The method further includes inserting, by the computer, dummy vias using a design-rule-checking utility separately from the inserting of the dummy metals.

Abstract: A method of inserting dummy metal and dummy via in an integrated circuit design. The method includes inserting, by a computer, dummy metals using a place and route tool, wherein the place and route tool has timing-awareness to improve a timing performance of the integrated circuit design. The method further includes inserting, by the computer, dummy vias using a design-rule-checking utility separately from the inserting of the dummy metals, wherein at least one of the dummy vias has a different size than at least another of the dummy vias.