Abstract: A system for displaying images is provided and includes a plurality of first signal lines, a plurality of second signal lines, a display area, and a first dummy line. The second signal lines are interlaced with the first signal lines. The display area comprises a plurality of display pixels. Each of the display pixels corresponds to the interlaced first signal line and second signal line. The first dummy line is disposed on a first side of the display area and interlaced with the second signal lines. A section of the first dummy line between every two adjacent second signal lines among the second signal lines has an opening.

Abstract: A system for displaying images includes a liquid crystal display panel including an array substrate. A color filter substrate is oppositely disposed to the array substrate and has a display region, a seal region surrounding the display region, and an edge region surrounding the seal region. A first transparent conductive pattern layer covers the display region of the color filter substrate to expose the seal region and the edge region, and faces the array substrate. A seal material layer is interposed between the array substrate and the color filter substrate and corresponds to the seal region, such that the seal material layer contacts at least a portion of the color filter substrate in the exposed seal region.

Abstract: A system for displaying images is provided and includes a plurality of first signal lines, a plurality of second signal lines, a display area, and a first dummy line. The second signal lines are interlaced with the first signal lines. The display area comprises a plurality of display pixels. Each of the display pixels corresponds to the interlaced first signal line and second signal line. The first dummy line is disposed on a first side of the display area and interlaced with the second signal lines. A section of the first dummy line between every two adjacent second signal lines among the second signal lines has an opening.

Abstract: A reflective and a transflective liquid crystal display device and a manufacturing method thereof are provided. The manufacturing method includes the following steps. First, a substrate structure of a reflective or a transflective liquid crystal display device is provided. Next, a reflection layer is formed over the substrate structure, a protection layer is formed over the reflection layer, and a photoresist layer is formed over the protection layer. Then, the photoresist layer is patterned to form a patterned photoresist layer, the protection layer is patterned to form a patterned protection layer, and the reflection layer is patterned to form a patterned reflection layer. Thereafter, the patterned photoresist layer is removed.

Abstract: Systems for displaying images and methods of fabricating are provided. A representative system incorporates a transflective thin film transistor liquid crystal display (TFT-LCD) panel having a plurality of subpixels. The display panel comprises a first substrate with a transparent electrodeformed thereon, a reflective electrode on the transparent electrode, a second substrate opposite the first substrate, a liquid crystal layer between the first substrate and the second substrate. The panel also exhibits at least one of: the reflective electrode and the transparent electrode overlap by substantially between 100 and 1000 square micrometers; the reflective electrode and the transparent electrode overlap such that a ratio of an area of overlap of the reflective electrode and the transparent electrode to an area of a corresponding subpixel is substantially between 0.05 and 0.12; and a ratio of an area of the transparent electrode to an area of a corresponding subpixel is substantially between 0.5 and 0.6.

Abstract: A reflective and a transflective liquid crystal display device and a manufacturing method thereof are provided. The manufacturing method includes the following steps. First, a substrate structure of a reflective or a transflective liquid crystal display device is provided. Next, a reflection layer is formed over the substrate structure, a protection layer is formed over the reflection layer, and a photoresist layer is formed over the protection layer. Then, the photoresist layer is patterned to form a patterned photoresist layer, the protection layer is patterned to form a patterned protection layer, and the reflection layer is patterned to form a patterned reflection layer. Thereafter, the patterned photoresist layer is removed.

Abstract: A method for making self-aligned contacts on a semiconductor substrate using a hard mask. After the transistor is formed, a blanket insulating layer is formed on said semiconductor substrate. A hard mask having openings on the blanket insulating layer is formed over the insulating layer. The openings overlay the source/drain region and part of the gate electrode structure. Using the patterned hard mask, the insulating layer is etched to the gate electrode protecting layer. Then self-aligned contacts is completed by etching the insulating layer to expose the source/drain regions using the gate electrode protecting layer and the insulating sidewall spacers as the mask.

Abstract: The present invention includes forming polysilicon plugs between the gate structures and word lines in a BPSG layer formed on the gate structures and the word lines. A polysilicon layer, a tungsten silicide layer and a silicon oxide layer are sequentially formed on the BPSG layer. Then, the multi-layers are etched to the surface of the BPSG layer. Next, the BPSG layer is slightly etched to expose the polysilicon plug. Oxide spacers are formed on the sidewalls of the layers. A silicon nitride layer is formed over the bit lines, oxide spacers and on the polysilicon plugs. An oxide layer is formed on the silicon nitride layer. Subsequently, the oxide layer is patterned to form node contact holes. An etching is used to etch the silicon nitride layer. A first conductive layer is formed along the surface of the oxide layer, the contact holes. The top portion of the first conductive layer is removed. The oxide layer is removed to expose the silicon nitride layer.

Abstract: A method for avoiding micro-loading effect during etching is disclosed. The method comprises the steps of: providing a semiconductor substrate with a layer to be patterned and etched formed thereover; forming a masking layer over the layer to be patterned; defining a row pattern in the masking layer, the row pattern comprising a plurality of rectangles and a plurality of connecting bars, each of the connecting bars connecting two of the rectangles; and removing a portion of the layer to be patterned, to form a patterned layer with a recessed channel, by using the masking layer as a mask with the row pattern.

Abstract: A process for fabricating an interconnect structure, featuring contact of the interconnect structure, to an exposed side of an underlying conductive plug structure, where the conductive plug structure is used to communicate with an active device region in a semiconductor substrate, has been developed. The process features the use of simple photolithographic patterns, such as a stripe opening, exposing a group of gate structures, and a group of spaces, located between the gate structures, to be used for subsequent contact plug formation. This is in contrast to conventional processing, in which a more difficult photolithographic procedure is used to create smaller, individual openings, to individual spaces between gate structures. In addition this invention features a self-aligned opening, exposing only a side of a contact plug structure.

Abstract: A process for creating a crown shaped storage node structure, for a DRAM capacitor structure, featuring the use of a silicon oxynitride layer, underlying the crown shaped storage node structure, has been developed. A silicon oxynitride layer is placed overlying the interlevel dielectric layers that used to protect underlying DRAM elements, and placed underlying a capacitor opening in an overlying insulator layer. A selective RIE procedure is used to create the capacitor opening, in an insulator layer, with the RIE procedure terminating at the exposure of the underlying silicon oxynitride layer. After creation of the crown shaped storage node structure, in the capacitor opening, overlying the silicon oxynitride layer at the bottom of the capacitor opening, the insulator layer used for formation of the capacitor opening, is selectively removed from the regions of silicon oxynitride layer, not covered by the overlying crown shaped storage node structure, using wet etch procedures.

Abstract: A method for forming a self-aligned contact, (SAC), opening, for a semiconductor device, has been developed. The process features the formation of partial silicon nitride spacers, on the sides of polycide gate structures, via a partial anisotropic RIE procedure, applied to a silicon nitride layer, also resulting in a thin layer of silicon nitride remaining on regions between polycide gate structures. After deposition of an overlying insulator layer, a two step, anisotropic RIE procedure is used to create the SAC opening in the insulator layer, and in the underlying, thin silicon nitride layer. The first step, of the two step, SAC opening procedure, selectively removes first insulator layer, while the second step, of the two step, SAC opening procedure, selectively removes the thin silicon nitride layer.

Abstract: The present invention is a method for improviding an oxide etching process by using a nitrogen-based plasma. An additional nitrogen-based plasma step is used to inhibit or delay the formation of observed residual bubbles during a dry etching process. The method comprises the steps of etching the oxide layer by reactive ion etching and immersing the oxide layer in a nitrogen plasma.

Abstract: DRAM cells having self-aligned node-contacts-to-bit lines with tungsten landing plug contacts for reduced aspect ratio contact openings and via holes is achieved. A planar insulating layer is formed, and openings for bit line contacts, node contacts, and landing plugs on the chip periphery are concurrently etched. A W/TiN layer is patterned to form bit lines, capacitor node, and multilevel contact landing plugs on the DRAM chip. The landing plugs reduce the aspect ratio of the openings for the multilevel contacts. Bit line sidewall spacers are formed, and a BPSG is deposited and planarized. Capacitor openings are etched in the BPSG aligned over the node contacts. A conformal conducting layer is deposited, and a polymer is deposited and planarized. The polymer and the conducting layer are polished back to complete the capacitor bottom electrodes in the capacitor openings. The polymer is removed.