Patents by Inventor Hung-Yi Yeh

Hung-Yi Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240088267
    Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yi PENG, Chih Chieh YEH, Chih-Sheng CHANG, Hung-Li CHIANG, Hung-Ming CHEN, Yee-Chia YEO
  • Publication number: 20240070416
    Abstract: A reading method and a reading device for a two-dimensional code. The method includes: capturing a two-dimensional code image through an image capturing device; detecting an outer frame and a position mark of a two-dimensional code in a skewed state in the two-dimensional code image; restoring the two-dimensional code in the skewed state to a default state; and performing a default operation according to the two-dimensional code in the default state.
    Type: Application
    Filed: November 15, 2022
    Publication date: February 29, 2024
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Chin-Hao Yeh, Chin-Wen Lin, Hung-Yi Lin
  • Publication number: 20060060377
    Abstract: In manufacturing a multi-layer printed circuit board (PCB), different processes are employed for forming inner and outer circuit layers of the PCB. Particularly, second and third inner circuit layers of the multi-layer PCB are formed with the resin build-up process through liquid epoxy coating or dry film type epoxy laminating to enable refinement of circuits provided thereon, and two outer circuit layers of the multi-layer PCB are formed on copper clad and insulating dielectric with the lamination process to improve the thermal resistance, copper peel strength, structural stiffness, thermal stress reliability, and size stability of the completed PCB. The multi-layer PCB manufactured with two different processes has improved quality and reliability, and may be manufactured at reduced cost.
    Type: Application
    Filed: November 10, 2005
    Publication date: March 23, 2006
    Inventors: Cheng-Hsien Chou, Hung-Yi Yeh, Chia-Hung Lin, Jia-Ren Liang
  • Publication number: 20050042852
    Abstract: A method for applying the solder mask onto solder pad spacings of a printed circuit board, mainly referring to the use of an ink-jet printer for printing the solder mask at the dense solder pad area on a printed circuit board, so as to prevent the solder mask from being coated onto solder pads in the dense solder pad area, thus improving the reliability of assembling processes for electronic products, and further providing merits of minimizing clearances between the solder mask and solder pads and increasing the adhesion of the solder mask.
    Type: Application
    Filed: August 19, 2003
    Publication date: February 24, 2005
    Applicant: Unitech Printed Circuit Board Corp.
    Inventors: Cheng-Hsien Chou, Hung-Yi Yeh, Smoon Lin
  • Publication number: 20050016762
    Abstract: In manufacturing a multi-layer printed circuit board (PCB), different processes are employed for forming inner and outer circuit layers of the PCB. Particularly, second and third inner circuit layers of the multi-layer PCB are formed with the resin build-up process through liquid epoxy coating or dry film type epoxy laminating to enable refinement of circuits provided thereon, and two outer circuit layers of the multi-layer PCB are formed on copper clad and insulating dielectric with the lamination process to improve the thermal resistance, copper peel strength, structural stiffness, thermal stress reliability, and size stability of the completed PCB. The multi-layer PCB manufactured with two different processes has improved quality and reliability, and may be manufactured at reduced cost.
    Type: Application
    Filed: July 22, 2003
    Publication date: January 27, 2005
    Inventors: Cheng-Hsien Chou, Hung-Yi Yeh, Chia-Hung Lin, Jia-Ren Liang