Patents by Inventor Hung-Yih Hsieh

Hung-Yih Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7096439
    Abstract: An intellectual property (IP) merge system includes first and second storage device portions, a graphical user interface server, and an IP server. A user inputs integrated circuit (IC) configuration information into the first storage device by way of a network. The second storage device portion stores cell library IP data. The graphical user interface server serves at least one page by way of the network. The page enables the user to request an IP merge operation based on the IC configuration information and the cell library IP data. The IP server performs the IP merge operation in response to the request by the user.
    Type: Grant
    Filed: May 21, 2003
    Date of Patent: August 22, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng Mao Tsai, Hung-Yih Hsieh
  • Publication number: 20040237054
    Abstract: An intellectual property (IP) merge system includes first and second storage device portions, a graphical user interface server, and an IP server. A user inputs integrated circuit (IC) configuration information into the first storage device by way of a network. The second storage device portion stores cell library IP data. The graphical user interface server serves at least one page by way of the network. The page enables the user to request an IP merge operation based on the IC configuration information and the cell library IP data. The IP server performs the IP merge operation in response to the request by the user.
    Type: Application
    Filed: May 21, 2003
    Publication date: November 25, 2004
    Inventors: Cheng Mao Tsai, Hung-Yih Hsieh
  • Patent number: 5801678
    Abstract: A high-speed real-time bi-linear interpolation apparatus is disclosed for scaling an old M.times.M' image into a new N.times.N' image by which the pixel value of a new pixel q(x', y') is interpolated from the pixel values of four immediately enclosing old pixels, p(x, y), p(x+1, y), p(x, y+1), and p(x+1, y+1). The fast bi-linear interpolation apparatus comprises: (a) a counter for obtaining the x-directional and y-directional pixel counts of the new pixel (x', y'), designated as n and n', respectively; (b) an accumulator for calculating the x-directional and y-directional pixel counts of the he old pixel (x, y), designated as m and m', respectively; (c) logic circuits associated with the accumulator means for calculating x-directional and y-directional interpolation parameters Acc and Acc', respectively, wherein Acc is the numerator of fraction after the division of (n.multidot.M.div.N), and Acc' is the numerator of fraction after the division (n'.multidot.M'.div.
    Type: Grant
    Filed: April 26, 1996
    Date of Patent: September 1, 1998
    Assignee: Industrial Technology Research Institute
    Inventors: Wei-Lun Huang, Kimbo Hsiao, Hung-Yih Hsieh