Abstract: An apparatus includes a laminate, the laminate including a dielectric layer having a first surface and a second surface opposed to the first surface, and a conductive layer forming a circuit element overlying the first surface of the dielectric layer. The apparatus further includes a magnetic layer over the conductive layer. A first edge surface of the magnetic layer is coplanar with a first edge surface of the laminate, and a second edge surface of the magnetic layer is coplanar with a second edge surface of the laminate.

Abstract: A method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. The second redistribution lines are formed using the alignment mark for alignment.

Abstract: A method of initializing a computer system equipped with a debugging system. The computer system has a ROM coupled to an expansion bus and stores a first BIOS code, and the debugging system is coupled to a peripheral bus. The method comprises the steps of routing data requests directed to the ROM to a local bus by a CPU, transferring the data requests from the local bus to the peripheral bus via a first bridge, switching a second bridge into normal mode wherein the second bridge is enabled to respond to data requests on the peripheral bus with the first BIOS code stored in ROM to be loaded in the CPU, and switching the second bridge to debugging mode wherein the second bridge is disabled from responding to data requests on the peripheral bus, instead, the debugging system responds to data requests with the second BIOS code to be loaded in the CPU.

Abstract: An apparatus for monitoring the state of computer system resources. According to the invention, the apparatus includes bus interface logic and a queue. The bus interface logic is used to interface with a serial bus and parse a bitstream through the serial bus into a command and an address. Also, the apparatus includes bridge logic, an arbitrator and a decoder. The decoder is used to decode the command. If the command represents a predetermined request for access to a resource bus, the decoder passes the predetermined request associated with the address to the queue. Whenever the predetermined request occurs, the arbitrator grants the resource bus to the predetermined request and allows the queue to output the predetermined request as well as the associated address. The bridge logic is provided to transfer data to and from computer system resources according to the predetermined request and the address.

Abstract: A method of initializing a computer system equipped with a debugging system. The computer system has a CPU, a local, peripheral and expansion bus, a first and second bridge, and a ROM coupled to the expansion bus and store a first BIOS code, and the debugging system is coupled to the peripheral bus. The method including the steps of operating the CPU in a normal mode wherein first data requests directed to the ROM are routed to the local bus by the CPU, operating the CPU in a debugging mode wherein second data requests directed to the debugging system are routed to the local bus bye the CPU, transferring the first or second data requests from the local bus to the peripheral bus by the first bridge, responding by the second bridge or debugging system to the data requests with the first or second BIOS code to be loaded in the CPU according to the direction of the data request.

Abstract: A method of initializing a computer system equipped with a debugging system. The computer system has a ROM coupled to an expansion bus and stores a first BIOS code, and the debugging system is coupled to a peripheral bus. The method comprises the steps of routing data requests directed to the ROM to a local bus by a CPU, transferring the data requests from the local bus to the peripheral bus via a first bridge, switching a second bridge into normal mode wherein the second bridge is enabled to respond to data requests on the peripheral bus with the first BIOS code stored in ROM to be loaded in the CPU, and switching the second bridge to debugging mode wherein the second bridge is disabled from responding to data requests on the peripheral bus, instead, the debugging system responds to data requests with the second BIOS code to be loaded in the CPU.

Abstract: An apparatus for monitoring the state of computer system resources. According to the invention, the apparatus includes bus interface logic and a queue. The bus interface logic is used to interface with a serial bus and parse a bitstream through the serial bus into a command and an address. Also, the apparatus includes bridge logic, an arbitrator and a decoder. The decoder is used to decode the command. If the command represents a predetermined request for access to a resource bus, the decoder passes the predetermined request associated with the address to the queue. Whenever the predetermined request occurs, the arbitrator grants the resource bus to the predetermined request and allows the queue to output the predetermined request as well as the associated address. The bridge logic is provided to transfer data to and from computer system resources according to the predetermined request and the address.

Abstract: The present invention provides a multi-conditioner arrangement of a CMP system. The CMP system according to the present invention comprises a polishing table, a polishing pad positioned on the polishing table, a plurality of carrier heads on the polishing pad functioning in holding semiconductor wafers, and a plurality of conditioners positioned between the two neighboring carrier heads on the polishing pad for recovering the surface texture of the polishing pad. Herein, a plurality of conditioners are in a one-to-one arrangement to a plurality of carrier heads, each conditioner producing a back and forth motion in a radiant direction. Therefore, the lifetime of the polishing pad is extended, the wafer-to-wafer difference is reduced, and spatial coverage is increased.