Patents by Inventor Hung-Yu Yeh
Hung-Yu Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240106104Abstract: An electronic device includes a device body and an antenna module disposed in the device body and including a conductive structure and a coaxial cable including a core wire, a shielding layer wrapping the core wire, and an outer jacket wrapping the shielding layer. The conductive structure includes a structure body and a slot formed on the structure body and penetrating the structure body in a thickness direction of the structure body. A section of the shielding layer extends from the outer jacket and is connected to the structure body. A physical portion of the structure body and the section of the shielding layer are respectively located on two opposite sides of the slot in a width direction of the slot. A section of the core wire extends from the section of the shielding layer and overlaps the slot and the physical portion in the thickness direction.Type: ApplicationFiled: September 8, 2023Publication date: March 28, 2024Applicant: COMPAL ELECTRONICS, INC.Inventors: Hung-Yu Yeh, Shih-Chia Liu, Yen-Hao Yu, Li-Chun Lee, Chih-Heng Lin, Jui-Hung Lai
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Publication number: 20230378266Abstract: A device comprise a first semiconductor channel layer over a substrate, a second semiconductor channel layer over the first semiconductor channel layer, and source/drain epitaxial structures on opposite sides of the first semiconductor channel layer and opposite sides of the second semiconductor channel layer. A compressive strain in the second semiconductor channel layer is greater than a compressive strain in the first semiconductor channel layer. The source/drain epitaxial structures each comprise a first region interfacing the first semiconductor channel layer and a second region interfacing the second semiconductor channel layer, and the first region has a composition different from a composition of the second region.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Chung-En TSAI, Chia-Che CHUNG, Chee-Wee LIU, Fang-Liang LU, Yu-Shiang HUANG, Hung-Yu YEH, Chien-Te TU, Yi-Chun LIU
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Patent number: 11776998Abstract: A device comprises a plurality of nanosheets, source/drain stressors, and a gate structure wrapping around the nanosheets. The nanosheets extend in a first direction above a semiconductor substrate and are arranged in a second direction substantially perpendicular to the first direction. The source/drain stressors are on either side of the nanosheets. Each of the source/drain stressors comprises a first epitaxial layer and a second epitaxial layer over the first epitaxial layer. The first and second epitaxial layers are made of a Group IV element and a Group V element. An atomic ratio of the Group V element to the Group IV element in the second epitaxial layer is greater than an atomic ratio of the Group V element to the Group IV element in the first epitaxial layer.Type: GrantFiled: January 24, 2022Date of Patent: October 3, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Chung-En Tsai, Chia-Che Chung, Chee-Wee Liu, Fang-Liang Lu, Yu-Shiang Huang, Hung-Yu Yeh, Chien-Te Tu, Yi-Chun Liu
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Publication number: 20230253500Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm?3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.Type: ApplicationFiled: April 17, 2023Publication date: August 10, 2023Inventors: Huang-Siang LAN, CheeWee Liu, Chi-Wen Liu, Shih-Hsien Huang, I-Hsieh WONG, Hung-Yu YEH, Chung-En TSAI
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Patent number: 11631768Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm?3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.Type: GrantFiled: July 1, 2019Date of Patent: April 18, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Huang-Siang Lan, CheeWee Liu, Chi-Wen Liu, Shih-Hsien Huang, I-Hsieh Wong, Hung-Yu Yeh, Chung-En Tsai
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Patent number: 11609185Abstract: A portable ring-type fluorescence optical system for observing microfluidic channel and an operating method thereof are disclosed. The portable ring-type fluorescence optical system includes a photographic chip, a first polarizer, an objective lens, a ring-type fluorescent light source, a biological sample on a microfluidic chip, a second polarizer and a bottom illumination light source arranged in order from top to bottom. The ring-type fluorescent light source is used to generate a ring-type fluorescent light to the biological sample on the microfluidic chip. The objective lens is used to magnify a fluorescent image of the biological sample on the microfluidic chip to focus on the photographic chip. The first polarizer disposed under the photographic chip and the second polarizer disposed under the biological sample form a non-zero angle to each other to block reflected lights that the biological sample reflects the lights emitted by the bottom illumination light source.Type: GrantFiled: August 9, 2021Date of Patent: March 21, 2023Assignee: NATIONAL TSING HUA UNIVERSITYInventors: Sung-Yang Wei, Long Hsu, Hwan-You Chang, Huang-Ming Chen, Jen-Tsan Chi, Chung-Cheng Chou, Yuh-Cherng Lai, Hung-Yu Yeh, Ting-Chou Wei, Yun-Ting Yao, Cheng-Hsien Liu
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Patent number: 11515334Abstract: A MOSFET structure including stacked vertically isolated MOSFETs and a method for forming the same are disclosed.Type: GrantFiled: August 14, 2020Date of Patent: November 29, 2022Assignee: NATIONAL TAIWAN UNIVERSITYInventors: Yu-Shiang Huang, Hung-Yu Yeh, Wen Hung Huang, Chee-Wee Liu
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Publication number: 20220364995Abstract: A portable ring-type fluorescence optical system for observing microfluidic channel and an operating method thereof are disclosed. The portable ring-type fluorescence optical system includes a photographic chip, a first polarizer, an objective lens, a ring-type fluorescent light source, a biological sample on a microfluidic chip, a second polarizer and a bottom illumination light source arranged in order from top to bottom. The ring-type fluorescent light source is used to generate a ring-type fluorescent light to the biological sample on the microfluidic chip. The objective lens is used to magnify a fluorescent image of the biological sample on the microfluidic chip to focus on the photographic chip. The first polarizer disposed under the photographic chip and the second polarizer disposed under the biological sample form a non-zero angle to each other to block reflected lights that the biological sample reflects the lights emitted by the bottom illumination light source.Type: ApplicationFiled: August 9, 2021Publication date: November 17, 2022Applicant: NATIONAL TSING HUA UNIVERSITYInventors: Sung-Yang WEI, Long HSU, Hwan-You CHANG, Huang-Ming CHEN, Jen-Tsan CHI, Chung-Cheng CHOU, Yuh-Cherng LAI, Hung-Yu YEH, Ting-Chou WEI, Yun-Ting YAO, Cheng-Hsien LIU
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Publication number: 20220149172Abstract: A device comprises a plurality of nanosheets, source/drain stressors, and a gate structure wrapping around the nanosheets. The nanosheets extend in a first direction above a semiconductor substrate and are arranged in a second direction substantially perpendicular to the first direction. The source/drain stressors are on either side of the nanosheets. Each of the source/drain stressors comprises a first epitaxial layer and a second epitaxial layer over the first epitaxial layer. The first and second epitaxial layers are made of a Group IV element and a Group V element. An atomic ratio of the Group V element to the Group IV element in the second epitaxial layer is greater than an atomic ratio of the Group V element to the Group IV element in the first epitaxial layer.Type: ApplicationFiled: January 24, 2022Publication date: May 12, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Chung-En TSAI, Chia-Che CHUNG, Chee-Wee LIU, Fang-Liang LU, Yu-Shiang HUANG, Hung-Yu YEH, Chien-Te TU, Yi-Chun LIU
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Patent number: 11233120Abstract: The present disclosure generally relates to a gate-all-around (GAA) transistor. The GAA transistor may include regrown source/drain layers in source/drain stressors. Atomic ratio differences among the regrown source/drain layers are tuned to reduce strain mismatch among the semiconductor nanosheets. Alternatively, the GAA transistor may include strained channels formed using a layer stack of alternating semiconductor layers having different lattice constants.Type: GrantFiled: April 16, 2020Date of Patent: January 25, 2022Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Chung-En Tsai, Chia-Che Chung, Chee-Wee Liu, Fang-Liang Lu, Yu-Shiang Huang, Hung-Yu Yeh, Chien-Te Tu, Yi-Chun Liu
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Publication number: 20210328012Abstract: A method includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate; forming a dummy gate structure across the fin structure; etching portions of the fin structure to expose portions of the substrate; forming source/drain stressors over the exposed portions of the substrate; after forming the source/drain stressors, removing the dummy gate structure; after removing the dummy gate structure, removing the first semiconductor layers such that the second semiconductor layers are suspended between the source/drain stressors; and forming a gate structure to surround each of the suspended second semiconductor layers. The source/drain stressors each comprise a first source/drain layer and a second source/drain layer over the first source/drain layer. An atomic concentration of a Group IV element or a Group V element in the second source/drain layer is greater than that in the first source/drain layer.Type: ApplicationFiled: April 16, 2020Publication date: October 21, 2021Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Chung-En TSAI, Chia-Che CHUNG, Chee-Wee LIU, Fang-Liang LU, Yu-Shiang HUANG, Hung-Yu YEH, Chien-Te TU, Yi-Chun LIU
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Publication number: 20200373334Abstract: A MOSFET structure including stacked vertically isolated MOSFETs and a method for forming the same are disclosed.Type: ApplicationFiled: August 14, 2020Publication date: November 26, 2020Inventors: Yu-Shiang Huang, Hung-Yu Yeh, Wen Hung Huang, Chee Wee Liu
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Patent number: 10748935Abstract: A MOSFET structure including stacked vertically isolated MOSFETs and a method for forming the same are disclosed.Type: GrantFiled: October 4, 2018Date of Patent: August 18, 2020Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan UniversityInventors: Yu-Shiang Huang, Hung-Yu Yeh, Wen Hung Huang, Chee-Wee Liu
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Publication number: 20200006389Abstract: A MOSFET structure including stacked vertically isolated MOSFETs and a method for forming the same are disclosed.Type: ApplicationFiled: October 4, 2018Publication date: January 2, 2020Inventors: Yu-Shiang Huang, Hung-Yu Yeh, Wen Hung Huang, Chee-Wee Liu
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Publication number: 20190326437Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm?3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.Type: ApplicationFiled: July 1, 2019Publication date: October 24, 2019Inventors: Huang-Siang LAN, CheeWee LIU, Chi-Wen LIU, Shih-Hsien HUANG, I-Hsieh WONG, Hung-Yu YEH, Chung-En TSAI
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Patent number: 10340383Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm?3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.Type: GrantFiled: September 27, 2016Date of Patent: July 2, 2019Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Huang-Siang Lan, CheeWee Liu, Chi-Wen Liu, Shih-Hsien Huang, I-Hsieh Wong, Hung-Yu Yeh, Chung-En Tsai
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Patent number: 9923093Abstract: Semiconductor devices and methods of forming the same are provided. A first source/drain layer is formed over a substrate. A channel layer is formed over the first source/drain layer. A second source/drain layer is formed over the channel layer. The first source/drain layer, the channel layer, and the second source/drain layer are patterned to form a fin-shaped structure. A gate stack is formed on a sidewall of the fin-shaped structure. The fin-shaped structure is patterned to expose a top surface of the first source/drain layer.Type: GrantFiled: December 15, 2016Date of Patent: March 20, 2018Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan UniversityInventors: Chee Wee Liu, Samuel C. Pan, I-Hsieh Wong, Hung-Yu Yeh
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Patent number: 9812558Abstract: A method includes providing a substrate having a mesa, forming a first opening in the mesa, the first opening being surrounded by first inner sidewalls of the mesa exposed by the first opening. The method further includes etching from a first one of the first inner sidewalls of the mesa to form a first vertical recess, the first vertical recess having a wide end and a narrow end, with the narrow end defining a first vertically recessed channel region, and forming a first gate structure over the first vertically recessed channel region.Type: GrantFiled: March 22, 2017Date of Patent: November 7, 2017Assignees: National Taiwan University, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jhih-Yang Yan, Samuel C. Pan, Chee Wee Liu, Hung-Yu Yeh, Da-Zhi Zhang
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Publication number: 20170278968Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm? or less of a dopant, and a portion of the fin under the gate structure is a channel region.Type: ApplicationFiled: September 27, 2016Publication date: September 28, 2017Inventors: Huang-Siang LAN, CheeWee LIU, Chi-Wen LIU, Shih-Hsien HUANG, I-Hsieh WONG, Hung-Yu YEH, Chung-En TSAI
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Publication number: 20170194464Abstract: A method includes providing a substrate having a mesa, forming a first opening in the mesa, the first opening being surrounded by first inner sidewalls of the mesa exposed by the first opening. The method further includes etching from a first one of the first inner sidewalls of the mesa to form a first vertical recess, the first vertical recess having a wide end and a narrow end, with the narrow end defining a first vertically recessed channel region, and forming a first gate structure over the first vertically recessed channel region.Type: ApplicationFiled: March 22, 2017Publication date: July 6, 2017Inventors: Jhih-Yang Yan, Samuel C. Pan, Chee Wee Liu, Hung-Yu Yeh, Da-Zhi Zhang