Abstract: An integrated device includes a die having a contact pad and a solder cap electrically connected to the contact pad by a multi-layer interconnect pillar. The multi-layer interconnect pillar includes a base reinforcement layer, a cap reinforcement layer, and one or more solder layers disposed between the base reinforcement layer and the cap reinforcement layer.

Abstract: A thermal compression flip chip (TCFC) bump may be used for high performance products that benefit from a fine pitch. In one example, a new TCFC bump structure adds a metal pad underneath the TCFC copper pillar bump to cover the exposed aluminum bump pad. This new structure prevents the pad from corroding and reduces mechanical stress to the pad and underlying silicon dielectric layers enabling better quality and reliability and further bump size reduction. For example, a flip chip connection may include a substrate; a metal pad on a contact side of the substrate and a first passivation layer on the contact side of the substrate to protect the metal pad from corrosion.

Abstract: Disclosed are techniques for selectively boosting conductive pillar bumps. In an aspect, an apparatus includes a plurality of metal pads, a first set of boosting pads attached to a first set of the plurality of metal pads, a first set of conductive pillar bumps attached to the first set of boosting pads, a second set of conductive pillar bumps attached to a second set of the plurality of metal pads, wherein heights of the first set of conductive pillar bumps are shorter than heights of the second set of conductive pillar bumps, and wherein heights of the first set of boosting pads plus the heights of the first set of conductive pillar bumps are within a tolerance threshold of the heights of the second set of conductive pillar bumps, and solder attached to the first set of conductive pillar bumps and the second set of conductive pillar bumps.

Abstract: A package comprising a substrate and an integrated device coupled to the substrate through a plurality of pillar interconnects and a plurality of solder interconnects. The plurality of pillar interconnects includes a first pillar interconnect comprising a first cavity. The plurality of solder interconnects comprises a first solder interconnect located in the first cavity of the first pillar interconnect. A planar cross section that extends through the first cavity of the first pillar interconnect may comprise an O shape. The first pillar interconnect comprises a first pillar interconnect portion comprising a first width; and a second pillar interconnect portion comprising a second width that is different than the first width.

Abstract: A package comprising a substrate and an integrated device coupled to the substrate through a plurality of pillar interconnects and a plurality of solder interconnects. The plurality of pillar interconnects comprises a first pillar interconnect. The first pillar interconnect comprises a first pillar interconnect portion comprising a first width and a second pillar interconnect portion comprising a second width that is different than the first width.

Abstract: A package comprising a substrate and an integrated device coupled to the substrate through a plurality of pillar interconnects and a plurality of solder interconnects. The plurality of pillar interconnects includes a first pillar interconnect comprising a first cavity. The plurality of solder interconnects comprises a first solder interconnect located in the first cavity of the first pillar interconnect. A planar cross section that extends through the first cavity of the first pillar interconnect may comprise an O shape. The first pillar interconnect comprises a first pillar interconnect portion comprising a first width; and a second pillar interconnect portion comprising a second width that is different than the first width.

Abstract: A thermal compression flip chip (TCFC) bump may be used for high performance products that benefit from a fine pitch. In one example, a new TCFC bump structure adds a metal pad underneath the TCFC copper pillar bump to cover the exposed aluminum bump pad. This new structure prevents the pad from corroding and reduces mechanical stress to the pad and underlying silicon dielectric layers enabling better quality and reliability and further bump size reduction. For example, a flip chip connection may include a substrate; a metal pad on a contact side of the substrate and a first passivation layer on the contact side of the substrate to protect the metal pad from corrosion.

Abstract: A display including a back cover, a diffuser plate, a display panel, and a light source is provided. The back cover has a first supporting portion, a connecting portion and a second supporting portion. Two opposite ends of the connecting portion are connected to the first supporting portion and the second supporting portion respectively. The first supporting portion has a first surface, the second supporting portion has opposite second and third surfaces, and the first surface faces the second surface to form a containing space between the first surface, the connecting portion and the second surface. At least a part of a periphery of the diffuser plate is disposed in the containing space. The display panel is supported on the third surface. The light source is disposed on the back cover and adapted to provide a light beam to illuminate the display panel after passing through the diffuser plate.

Abstract: A display including a back cover, a diffuser plate, a display panel, and a light source is provided. The back cover has a first supporting portion, a connecting portion and a second supporting portion. Two opposite ends of the connecting portion are connected to the first supporting portion and the second supporting portion respectively. The first supporting portion has a first surface, the second supporting portion has opposite second and third surfaces, and the first surface faces the second surface to form a containing space between the first surface, the connecting portion and the second surface. At least a part of a periphery of the diffuser plate is disposed in the containing space. The display panel is supported on the third surface. The light source is disposed on the back cover and adapted to provide a light beam to illuminate the display panel after passing through the diffuser plate.

Abstract: A spread-spectrum clock generator includes a frequency comparator, for generating a compensation signal according to a reference signal and a frequency signal corresponding to an output frequency signal; a triangle-wave generator, for generating a triangle-wave signal according to a frequency control signal; an adder, coupled between the triangle-wave generator and the frequency comparator, for adding the compensation signal to the triangle-wave signal to generate an addition result; and a frequency synthesizer, coupled between the frequency comparator and the adder, for generating the output frequency signal to adjust the output frequency signal according to the addition result so as to reduce a shift of the output frequency signal.

Abstract: A chip structure having a redistribution layer includes: a chip with electrode pads disposed on an active surface thereof; a first passivation layer formed on the active surface and the electrode pads; a redistribution layer formed on the first passivation layer and having a plurality of wiring units, wherein each of the wiring units has a conductive pad, a conductive via and a conductive trace connecting the conductive pad and the conductive via, the conductive trace having at least a first through opening for exposing a portion of the first passivation layer; and a second passivation layer disposed on the first passivation layer and the redistribution layer, the second passivation layer being filled in the first through opening such that the first and second passivation layers are bonded to each other with the conductive trace sandwiched therebetween, thereby preventing delamination of the conductive trace from the second passivation layer.

Abstract: A spread-spectrum clock generator includes a frequency comparator, for generating a compensation signal according to a reference signal and a frequency signal corresponding to an output frequency signal; a triangle-wave generator, for generating a triangle-wave signal according to a frequency control signal; an adder, coupled between the triangle-wave generator and the frequency comparator, for adding the compensation signal to the triangle-wave signal to generate an addition result; and a frequency synthesizer, coupled between the frequency comparator and the adder, for generating the output frequency signal to adjust the output frequency signal according to the addition result so as to reduce a shift of the output frequency signal.

Abstract: A chip structure having a redistribution layer includes: a chip with electrode pads disposed on an active surface thereof; a first passivation layer formed on the active surface and the electrode pads; a redistribution layer formed on the first passivation layer and having a plurality of wiring units, wherein each of the wiring units has a conductive pad, a conductive via and a conductive trace connecting the conductive pad and the conductive via, the conductive trace having at least a first through opening for exposing a portion of the first passivation layer; and a second passivation layer disposed on the first passivation layer and the redistribution layer, the second passivation layer being filled in the first through opening such that the first and second passivation layers are bonded to each other with the conductive trace sandwiched therebetween, thereby preventing delamination of the conductive trace from the second passivation layer.

Abstract: A chip structure having a redistribution layer includes: a chip with electrode pads disposed on an active surface thereof; a first passivation layer formed on the active surface and the electrode pads; a redistribution layer formed on the first passivation layer and having a plurality of wiring units, wherein each of the wiring units has a conductive pad, a conductive via and a conductive trace connecting the conductive pad and the conductive via, the conductive trace having at least a first through opening for exposing a portion of the first passivation layer; and a second passivation layer disposed on the first passivation layer and the redistribution layer, the second passivation layer being filled in the first through opening such that the first and second passivation layers are bonded to each other with the conductive trace sandwiched therebetween, thereby preventing delamination of the conductive trace from the second passivation layer.

Abstract: A data management method for a USB device includes the steps of: sampling an analog input signal, and generating digital sample data corresponding to samples of the analog input signal; monitoring the number of the digital sample data generated within a predefined time interval; if the number of the digital sample data generated at the end of the predefined time interval matches a predetermined value, providing the digital sample data to a USB host; and if the number of the digital sample data generated at the end of the predefined time interval does not match the predetermined value, processing the digital sample data such that the number of the processed digital sample data matches the predetermined value, and providing the processed digital sample data to the USB host. A USB device including a data management module for implementing the data management method is also disclosed.

Abstract: A data synchronizer system includes at least two synchronizers for receiving a source pulse signal, a corresponding source clock, and a destination clock. At least two first memory units each have a destination clock input. A first switch has an input coupled to the source pulse signal and an output selectively coupled to a source pulse signal input of any one of the synchronizers. A second memory unit has an input coupled to the source data signal and a clock input coupled to the source clock. A second switch has an input coupled to an output of the second memory unit and an output selectively coupled to an input of any one of the first memory units. A generator is coupled to outputs of the synchronizers for outputting a data switch signal. A multiplexer has inputs coupled to outputs of the first memory units and outputs a destination data signal.

Abstract: A multi-pipe synchronizer system includes at least two synchronizers for receiving a source signal and corresponding source clock, and a destination clock. A switch is coupled to an input of each synchronizer for coupling the source signal to a selected synchronizer. A generator is coupled to an output of each synchronizer. The generator is for merging output of the synchronizers into a destination signal corresponding to the destination clock.

Abstract: A method for establishing communication between a USB having a first memory device and a second memory device and a host includes reading first USB identification data stored in the first memory device, determining if the USB device can communicate with the host based on the first USB identification data, and reading second USB identification data stored in the second memory device for establishing communication between the USB device and the host if the USB device cannot communicate with the host based on the first USB identification data.

Abstract: A composition of matter including a polymeric material which is either a plastic having carbon to carbon linkages or a binary blend of the plastic and starch, in which the plastic is at least 25% by weight of the binary blend; and an organic peracid compound dispersed in the polymeric material, the quantity of the peracid compound being 0.1 to 10% by weight of the polymeric material.