Abstract: An advanced semiconductor packaging structure includes a circuit board, a first chip disposed on the circuit board, and a second chip disposed on the first chip. The first chip has solder balls arranged at intervals and bonded to the circuit board, and first pads arranged at intervals. The second chip has second pads arranged at intervals. Each of the second pads is correspondingly bonded to each of the first pads. Each of the first and second pads comprises a graphene-copper composite material composed of graphene and copper. The graphene has a plurality of graphene microfilms. The graphene microfilms are dispersed and arranged in the gaps between adjacent copper atoms. The graphene microfilms have covalent bonds. Based on the total weight of the graphene-copper composite material, the graphene content is less than 3 wt %, and the oxygen content in the graphene-copper composite material is not greater than 10 ppm.

Abstract: A manufacturing method of a flip chip package structure is provided and has following steps: providing at least one silicon substrate having a connecting surface and at least one conductive base attached to the connecting surface; arranging a graphene copper layer covering the conductive base; laminating a photoresist layer on the connecting surface, etching the photoresist layer to form a cavity corresponding to the conductive base, and a portion of the graphene copper layer corresponding to the conductive base being exposed on a bottom of the cavity; electroplating a copper material on the graphene copper layer, and the copper material being accumulated in the cavity to form a copper pillar; removing the photoresist layer and the graphene copper layer covered by the photoresist layer.

Abstract: A manufacturing method of a flip chip package structure is provided and has following steps: providing at least one silicon substrate having a connecting surface and at least one conductive base attached to the connecting surface; arranging a graphene copper layer covering the conductive base; laminating a photoresist layer on the connecting surface, etching the photoresist layer to form a cavity corresponding to the conductive base, and a portion of the graphene copper layer corresponding to the conductive base being exposed on a bottom of the cavity; electroplating a copper material on the graphene copper layer, and the copper material being accumulated in the cavity to form a copper pillar; removing the photoresist layer and the graphene copper layer covered by the photoresist layer.

Abstract: A manufacturing method of a flip chip package structure is provided and has following steps: providing at least one silicon substrate having a connecting surface and at least one conductive base attached to the connecting surface; arranging a graphene copper layer covering the conductive base; laminating a photoresist layer on the connecting surface, etching the photoresist layer to form a cavity corresponding to the conductive base, and a portion of the graphene copper layer corresponding to the conductive base being exposed on a bottom of the cavity; electroplating a copper material on the graphene copper layer, and the copper material being accumulated in the cavity to form a copper pillar; removing the photoresist layer and the graphene copper layer covered by the photoresist layer.

Abstract: A method for generating analog schematic diagram based on building block classification and reinforcement learning is disclosed. First of all, deeper relationship features among devices with building block classification are obtained. Secondly, the device leveling gives an initial device placement topology resulting from the current/signal flows in the circuit netlist. Thirdly, reinforcement learning is applied to refine placement and routing topologies by embedding the building blocks and current/signal flow information into feature vectors. Pattern routing and maze routing algorithms are performed for local and global interconnections, respectively, followed by placement adjustment for density balancing and space minimization to obtain aesthetic analog circuit schematics.

Abstract: A package substrate structure includes a substrate, a metal base layer, a build-up film, a bonding layer, and a wiring unit. The metal base layer is disposed on the substrate. The build-up film is disposed on the metal base layer and is formed with trenches to expose the metal base layer. The build-up film includes an insulating material. The bonding layer is disposed on the build-up film and includes a graphene-metal composite. The graphene-metal composite includes a metal matrix, and a plurality of graphene nanostructures dispersed in the metal matrix and arranged among lattices of the metal matrix. The graphene nanostructures form covalent bonds with each other. The wiring unit is bonded to the build-up film through the bonding layer and fills the trenches so as to be electrically connected to the metal base layer. The wiring unit is formed with a wiring pattern on the build-up film.

Abstract: A manufacturing method of a flip chip package structure is provided and has following steps: providing at least one silicon substrate having a connecting surface and at least one conductive base attached to the connecting surface; arranging a graphene copper layer covering the conductive base; laminating a photoresist layer on the connecting surface, etching the photoresist layer to form a cavity corresponding to the conductive base, and a portion of the graphene copper layer corresponding to the conductive base being exposed on a bottom of the cavity; electroplating a copper material on the graphene copper layer, and the copper material being accumulated in the cavity to form a copper pillar; removing the photoresist layer and the graphene copper layer covered by the photoresist layer.

Abstract: The invention provides a manufacturing method for a multi-layer ceramic capacitor. the method includes: providing a plastic film; coating a layer of ceramic slurry on a side of the plastic film; coating a layer of copper paste on the layer of ceramic slurry to form a raw material, wherein the copper paste includes a copper powder and a graphene powder; and sintering the raw material at a temperature equal to or higher than 800° C. to sinter the layer of ceramic slurry into a ceramic dielectric layer and the copper paste into a copper electrode layer. The copper atoms are restricted by the graphene so that the copper atoms are confined in layer arrangement to improve flatness of copper atoms in the copper electrode layer.

Abstract: A molding method is provided. The method includes steps of: providing a mold having a male mold forming a column and a female mold forming a cavity; multiple ribs extending along a longitudinal direction of the column are formed on the column; inserting the male mold into the female mold to close the mold to make the column inserted in and separated from an inner surface of the cavity; filling a molten plastic material mixed with metal particles into the cavity so as to make the material fill a space between the column and the cavity; forming a molded heat transfer component covering the column by the solidified plastic material; taking out the molded heat transfer component with the column along the longitudinal direction of the column from the cavity; and separating the molded heat transfer component from the column along the longitudinal direction of the column.

Abstract: A radiative cooling structure for a printed circuit includes a circuit board and a cooling structure. A printed circuit is disposed on the circuit board. The printed circuit includes a plurality of printed leads and a thermal conductive area. The printed leads are connected to the thermal conductive area. A cooling structure covers the thermal conductive area. The cooling structure covers the thermal conductive area, and the cooling structure incudes a thermal radiation layer. Heat generated by heat sources on the circuit board is transferred to the thermal conductive area via the printed circuit. The cooling structure radiates the heat into surrounding space by radiation.

Abstract: A graphite heat sink includes a graphite heat conductive plate and a heat radiation layer. One side of the graphite heat conductive plate is used for absorbing heat from the heat source. The other side of the graphite heat conductive plate is covered by the heat radiation layer. Heat from the heat source is absorbed into the graphite heat conductive plate and then rapidly radiated from the heat radiation layer to dissipate.