Patents by Inventor Hung-Chih Wang
Hung-Chih Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11974228Abstract: An apparatus (e.g., an access point (AP) or a non-AP station (STA)) detects a non-primary subband of an operating bandwidth comprising a primary subband and the non-primary subband to be idle. The apparatus controls a transmit power in performing transmission on at least the non-primary subband.Type: GrantFiled: June 10, 2021Date of Patent: April 30, 2024Assignee: MediaTek Singapore Pte. Ltd.Inventors: Kai Ying Lu, Hung-Tao Hsieh, Yen-Shuo Lu, Chao-Chun Wang, James Chih-Shi Yee, Yongho Seok
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Package structure comprising buffer layer for reducing thermal stress and method of forming the same
Patent number: 11961777Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.Type: GrantFiled: June 27, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chih Chen, Chien-Hsun Lee, Chung-Shi Liu, Hao-Cheng Hou, Hung-Jui Kuo, Jung-Wei Cheng, Tsung-Ding Wang, Yu-Hsiang Hu, Sih-Hao Liao -
Publication number: 20240105480Abstract: A wafer storage elevator and method for detecting wafer position shift. The elevator includes a first storage elevator sidewall, a second storage elevator sidewall, and a storage seat positioned between the first and second storage elevator sidewalls. A first mirror block is coupled to a front side of the storage seat having a mirror positioned on a top surface of the block, and a second mirror block is coupled to the front side of the storage seat having a mirror that is positioned on the top surface of the second mirror block. The mirror of the first mirror block reflects a laser beam from an emission sensor to the second mirror block, and the mirror of the second mirror block reflects the laser beam from the mirror of the first mirror block to a receive sensor. A wafer misalignment is determined based upon an output of the receive sensor.Type: ApplicationFiled: January 4, 2023Publication date: March 28, 2024Inventors: Ming-Sze Chen, Yuan-Hsin Chi, Hung-Chih Wang, Sheng-Yuan Lin
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Publication number: 20240021416Abstract: A connect structure for semiconductor processing equipment includes a housing configured to mate a deformable pipe with a non-deformable pipe. The housing includes a first annular sidewall to receive the deformable pipe and a second annular sidewall defining a first thread structure. An annular bead is connected to the first annular sidewall to flexibly deform the deformable pipe toward the non-deformable pipe structure when the first thread structure rotatably engages a second thread structure of the non-deformable pipe.Type: ApplicationFiled: July 18, 2022Publication date: January 18, 2024Inventors: Ming-Sze Chen, Hung-Chih Wang, Yuan-Hsin Chi, Sheng-Yuan Lin
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Publication number: 20230373100Abstract: The present disclosure is directed to a transfer blade including a first end segment, a second end segment opposite to the first end segment, and an intermediate segment extending from the first end segment to the second end segment. The first end segment includes a first contact region and the second end segment includes a second contact region. The first and second contact regions are configured to contact locations of a surface of a workpiece that do not overlap or are not aligned with a sensitive area of the workpiece. The sensitive area of the workpiece may be an EUV frame or a reticle of the workpiece. A non-contact region extends continuously along the first end segment, the intermediate segment, and the second end segment, and the non-contact region overlaps the sensitive area of the workpiece and is spaced apart from the sensitive area of the workpiece.Type: ApplicationFiled: May 19, 2022Publication date: November 23, 2023Inventors: Chih-Wei CHOU, Sheng-Yuan LIN, Yuan-Hsin CHI, Hung-Chih WANG, Yu-Chi LIU
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Publication number: 20230207365Abstract: A wafer pod transfer assembly includes a wafer pod port to receive a wafer pod, a transfer axle coupled to the wafer pod port, a shaft receiver, a shaft coupled to the transfer axle and to the shaft receiver, a pin through the shaft receiver and through the shaft, wherein the pin comprises a first end and a second end, opposite the first end, and a pin buckle including a first loop and a second loop. The pin buckle is coupled to the pin, the first loop encircles the first end of the pin, and the second loop encircles the second end of the pin.Type: ApplicationFiled: March 6, 2023Publication date: June 29, 2023Inventors: Chih-Wei CHOU, Sheng-Yuan LIN, Yuan-Hsin CHI, Yin-Tun CHOU, Hung-Chih WANG, Yu-Chi LIU
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Patent number: 11600506Abstract: A wafer pod transfer assembly includes a wafer pod port to receive a wafer pod, a transfer axle coupled to the wafer pod port, a shaft receiver, a shaft coupled to the transfer axle and to the shaft receiver, a pin through the shaft receiver and through the shaft, wherein the pin comprises a first end and a second end, opposite the first end, and a pin buckle including a first loop and a second loop. The pin buckle is coupled to the pin, the first loop encircles the first end of the pin, and the second loop encircles the second end of the pin.Type: GrantFiled: July 22, 2021Date of Patent: March 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Chih-Wei Chou, Sheng-Yuan Lin, Yuan-Hsin Chi, Yin-Tun Chou, Hung-Chih Wang, Yu-Chi Liu
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Publication number: 20230065818Abstract: An apparatus for performing a deposition process on a semiconductor wafer includes a chamber, a wafer holder, and a shielding structure. The chamber contains a reaction area, the wafer holder is disposed in the chamber to hold the semiconductor wafer, and the reaction area is above the semiconductor wafer. The shielding structure is disposed in the chamber and isolates an inner sidewall of the chamber from the reaction area. The shielding structure includes a base member, a first member, and a second member. The base member is disposed between the inner sidewall of the chamber and the wafer holder. The first member is disposed on the base member and is windowless. The second member is disposed on the base member and within the first member, and the second member includes a sidewall provided with a first window to transfer the semiconductor wafer.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Wei Chou, Sheng-Yuan Lin, Yuan-Hsin Chi, Yin-Tun Chou, Hung-Chih Wang, Yu-Chi Liu
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Publication number: 20230068139Abstract: A clamp ring including an inner periphery of increased diameter at locations where inwardly extending tabs are not located reduces the risk a workpiece that is placed in close proximity to the clamp ring or which contacts the clamp ring during processing will stick to the clamp ring.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Inventors: Chih-Wei CHOU, Yuan-Hsin CHI, Yin-Tun CHOU, Hung-Chih WANG, Yu-Chi LIU, Chih-Ming WANG
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Publication number: 20230017955Abstract: A system and method for cleaning a preclean process chamber in between wafer processing. The internal pressure of the preclean process chamber is reduced to a first pressure and a first gas that consists of oxygen and an inert or noble gas, is introduced into the chamber. Plasma is generated within the preclean process chamber using the first gas at the first pressure. Internal pressure is then reduced to a second pressure, less than the first, and the first gas is continued into the chamber. Plasma is then generated using the first gas at the second pressure. Thereafter, a second gas, consisting of an oxygen-free inert or noble gas, is introduced into the chamber at the second pressure, following which plasma is generated within the chamber using only the second gas.Type: ApplicationFiled: February 24, 2022Publication date: January 19, 2023Inventors: Yu-Ting Tsai, Hung-Chih Wang, Hong-Ming Lo, Shao-Shuo Wu, Su-Yu Yeh
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Publication number: 20230013102Abstract: Methods of forming a semiconductor device structure are described. The method includes forming a first conductive feature including a conductive fill material over a substrate, forming an etch stop layer on the conductive fill material, forming an intermetallization dielectric on the etch stop layer, forming an opening in the etch stop layer and the intermetallization dielectric to expose a portion of the conductive fill material, forming a recess in the exposed portion of the conductive fill material, and the opening and the recess together form a rivet-shaped space. The method further includes forming a second conductive feature in the rivet-shaped space and forming a metal nitride layer over the intermetallization dielectric and the second conductive feature. The forming the metal nitride layer includes depositing the metal nitride layer and treating the metal nitride layer with a plasma treatment process.Type: ApplicationFiled: May 3, 2022Publication date: January 19, 2023Inventors: Hung-Chih WANG, Hsin-Jung CHANG, Chun-Chih LIN, Su-Yu YEH
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Publication number: 20220384220Abstract: A semiconductor processing station includes first and second chambers, and a cooling stage. The second chamber includes a cooling pipe disposed inside the second chamber, and an external pipe. The cooling pipe includes a first segment disposed along a sidewall of the second chamber, and a second segment disposed perpendicular to the first segment and located above a wafer carrier in the second chamber. An end of the second segment is connected to an end of the first segment. The external pipe is connected to the second segment distal from the end of the second segment to provide a fluid to flow through the cooling pipe from an exterior to an interior of the second chamber. The fluid discharges toward the wafer carrier through the first segment. The first chamber is surrounded by the second chamber and the cooling stage, and communicates between the cooling stage and the second chamber.Type: ApplicationFiled: August 10, 2022Publication date: December 1, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Wei Lu, Hon-Lin Huang, Hung-Chih Wang
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Publication number: 20220344191Abstract: A wafer pod transfer assembly is provided. The wafer pod transfer assembly includes a wafer pod port to receive a wafer pod, a transfer axle coupled to the wafer pod port, a shaft receiver, a shaft coupled to the transfer axle and to the shaft receiver, a pin through the shaft receiver and through the shaft, wherein the pin comprises a first end and a second end, opposite the first end, and a pin buckle including a first loop and a second loop. The pin buckle is coupled to the pin, the first loop encircles the first end of the pin, and the second loop encircles the second end of the pin.Type: ApplicationFiled: July 22, 2021Publication date: October 27, 2022Inventors: Chih-Wei CHOU, Sheng-Yuan Lin, Yuan-Hsin Chi, Yin-Tun Chou, Hung-Chih Wang, Yu-Chi Liu
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Patent number: 11462425Abstract: A semiconductor processing station includes first and second chambers, and a cooling stage. The second chamber includes a cooling pipe disposed inside the second chamber, and an external pipe. The cooling pipe includes a first segment disposed along a sidewall of the second chamber, and a second segment disposed perpendicular to the first segment and located above a wafer carrier in the second chamber. An end of the second segment is connected to an end of the first segment. The external pipe is connected to the second segment distal from the end of the second segment to provide a fluid to flow through the cooling pipe from an exterior to an interior of the second chamber. The fluid discharges toward the wafer carrier through the first segment. The first chamber is surrounded by the second chamber and the cooling stage, and communicates between the cooling stage and the second chamber.Type: GrantFiled: June 24, 2020Date of Patent: October 4, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Wei Lu, Hon-Lin Huang, Hung-Chih Wang
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Publication number: 20220301947Abstract: A deposition tool includes a power cable pedestal including a pedestal body with a first surface and a second surface and a guide hole that extends through the pedestal body from the first surface to the second surface, where at least a portion of a sidewall of the guide hole has a slanted surface, and where the pedestal body is formed from a first material with a melting point that is higher than a melting point of Polyoxymethylene (POM). The deposition tool includes a bushing arranged over the guide hole, where the bushing is formed from a second material with a melting point that is higher than the melting point of POM.Type: ApplicationFiled: June 11, 2021Publication date: September 22, 2022Inventors: Chih-Wei CHOU, Yuan-Hsin CHI, Sheng-Yuan LIN, Yin-Tun CHOU, Hung-Chih WANG, Yu-Chi LIU
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Publication number: 20210110161Abstract: An interactive try-on system and method for eyeglass frame, which utilizes an augmented reality module to combine an image of the consumer itself with images of various eyeglass frames. The consumer can directly see the eyeglass frame on the display device, and decide which eyeglass frame to buy, and then inform the service staff the eyeglass frame that you want to buy, whereby consumers can try a variety of different eyeglass frames.Type: ApplicationFiled: September 23, 2020Publication date: April 15, 2021Inventor: Hung-Chih Wang
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Patent number: 10801031Abstract: A shuttle vector is provided which can be manipulated in various kinds of host cells, thereby providing a novel tool for the field of genetic engineering. Also provided are a prokaryotic host cell and a kit including said shuttle vector, so as to construct expression vectors which contain the target gene using the shuttle vector, thereby producing proteins in various host cells with one single vector.Type: GrantFiled: September 20, 2018Date of Patent: October 13, 2020Assignee: AGRICULTURAL TECHNOLOGY RESEARCH INSTITUTEInventors: Jiunn-Horng Lin, Jyh-Perng Wang, Zeng-Weng Chen, Wen-Zheng Huang, Hung-Chih Wang, Shih-Ling Hsuan
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Publication number: 20200321230Abstract: A semiconductor processing station includes first and second chambers, and a cooling stage. The second chamber includes a cooling pipe disposed inside the second chamber, and an external pipe. The cooling pipe includes a first segment disposed along a sidewall of the second chamber, and a second segment disposed perpendicular to the first segment and located above a wafer carrier in the second chamber. An end of the second segment is connected to an end of the first segment. The external pipe is connected to the second segment distal from the end of the second segment to provide a fluid to flow through the cooling pipe from an exterior to an interior of the second chamber. The fluid discharges toward the wafer carrier through the first segment. The first chamber is surrounded by the second chamber and the cooling stage, and communicates between the cooling stage and the second chamber.Type: ApplicationFiled: June 24, 2020Publication date: October 8, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Wei Lu, Hon-Lin Huang, Hung-Chih Wang
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Patent number: 10763140Abstract: A semiconductor processing station including a central transfer chamber, a load lock chamber disposed adjacent to the central transfer chamber, and a cooling stage disposed adjacent to the load lock chamber and the central transfer chamber is provided. The load lock chamber is adapted to contain a wafer carrier including a plurality of wafers. The central transfer chamber communicates between the cooling stage and the load lock chamber to transfer a wafer of the plurality of wafers between the cooling stage and the load lock chamber.Type: GrantFiled: October 14, 2018Date of Patent: September 1, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Wei Lu, Hon-Lin Huang, Hung-Chih Wang
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Publication number: 20190093113Abstract: The present application provides a shuttle vector which can be manipulated in various kinds of host cells, thereby providing a novel tool for the field of genetic engineering. On the other hand, the present application further provides a prokaryotic host cell and a kit comprising said shuttle vector, so as to construct expression vectors which contain the target gene using the shuttle vector, thereby producing proteins in various host cells with one single vector.Type: ApplicationFiled: September 20, 2018Publication date: March 28, 2019Applicant: Agricultural Technology Research InstituteInventors: Jiunn-Horng LIN, Jyh-Perng WANG, Zeng-Weng CHEN, Wen-Zheng HUANG, Hung-Chih WANG, Shih-Ling HSUAN