Abstract: A memory device, including: a cell array comprising a plurality of memory cells, wherein each memory cell from among the plurality of memory cells is connected to a corresponding word line from among a plurality of word lines and a corresponding bit line from among of a plurality of bit lines; a driver circuit configured to output a first driving voltage to a first power line; a compensation circuit connected to the first power line; a decoder circuit configured to program a memory cell by selecting a word line and a bit line based on an address, and providing a charge from the first power line, wherein the charge is floated through the selected word line or the selected bit line; and a control circuit configured to control the compensation circuit to adjust an amount of the charge based on the address.

Abstract: A semiconductor memory device includes a semiconductor substrate; a plurality of word line layers on the semiconductor substrate, each word line layer of the plurality of word line layers including an insulating line and a word line; a plurality of insulating layers in spaces between the plurality of word line layers, the plurality of insulating layers being apart from each other in a vertical direction on the semiconductor substrate; a channel structure extending in the vertical direction on the semiconductor substrate, the channel structure including a channel region and a gate dielectric layer surrounding the channel region; and a bit line on the channel structure, the bit line extending in a first horizontal direction perpendicular to the vertical direction and being connected to the channel structure, wherein the word line of each word line layer of the plurality of word line layers has a meandering shape.