Patents by Inventor Hunt A. Sutherland

Hunt A. Sutherland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7873581
    Abstract: A method and system for determining the reliability and a remaining time before failure for a DC motor system is provided. The method and system may determine the reliability and a remaining time before failure with a statistical confidence. The method and system may includes acquiring historical motor data, obtaining operational data, performing failure analysis, developing a causal network, and performing an integrated causal network and reliability analysis of the DC motor system.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: January 18, 2011
    Assignee: General Electric Company
    Inventors: Greg L. Flickinger, Gary J. Chmiel, Hunt A. Sutherland
  • Publication number: 20090096406
    Abstract: A method and system for determining the reliability and a remaining time before failure for a DC motor system is provided. The method and system may determine the reliability and a remaining time before failure with a statistical confidence. The method and system may includes acquiring historical motor data, obtaining operational data, performing failure analysis, developing a causal network, and performing an integrated causal network and reliability analysis of the DC motor system.
    Type: Application
    Filed: October 15, 2007
    Publication date: April 16, 2009
    Inventors: Greg L. Flickinger, Gary J. Chmiel, Hunt A. Sutherland
  • Patent number: 5600310
    Abstract: A household appliance having a serial bus control system includes a system controller, a plurality of slave nodes, and a serial bus connector. Each slave node is a sensor, an actuator, or the like, that is coupled to the serial bus connector and is responsive to a particular slave node address code generated by a master communications module that is part of the system controller. The serial bus connector is a loop of conductor which is attached at each end of the loop to the master communication module, with the slave nodes coupled to the loop at intermediate positions along the loop. The master communications module includes an interrogation circuit for generating digital transmissions to one or more of said slave node address codes and a receiver circuit for receipt of digital transmissions from the slave nodes coupled to said serial bus connector.
    Type: Grant
    Filed: December 2, 1994
    Date of Patent: February 4, 1997
    Assignee: General Electric Company
    Inventors: Walter Whipple, III, Hunt A. Sutherland
  • Patent number: 5552712
    Abstract: A system for testing the integrity of critical circuitry, lines and wires employs a differential amplifier having an input resistance R.sub.in and a feedback loop with a resistance R.sub.fb. The critical wires being tested must be a signal wire series connected to a resistance R.sub.S, which is in turn series connected to a return wire. A test voltage source is connected to the noninverting input of the differential amplifier. The signal wire is connected to the inverting input of the differential amplifier. The test voltage source is activated by a test control unit. When activated, the test voltage source provides two distinct outputs allowing computation of a test gain in the presence of other functional signals. The test control unit measures the output V.sub.out of the differential amplifier and computes the value of the test gain. A break in either the signal wire or the return wire will result in a test gain of 1. If the signal and return wires are shorted, the test gain will be 1+R.sub.fb /R.sub.in.
    Type: Grant
    Filed: February 15, 1995
    Date of Patent: September 3, 1996
    Assignee: General Electric Company
    Inventors: Michael P. Weir, Hunt A. Sutherland
  • Patent number: 5532601
    Abstract: A system for testing the integrity of critical circuitry, lines and wires employs a differential amplifier having an input resistance R.sub.in and a feedback loop with a resistance R.sub.fb. The critical wires being tested must be a signal wire series connected to a resistance R.sub.s, which is in turn series connected to a return wire. A test voltage source is connected to the noninverting input of the differential amplifier. The signal wire is connected to the inverting input of the differential amplifier. The test voltage source is activated by a test control unit. When activated, the test voltage source provides two distinct outputs allowing computation of a test gain in the presence of other functional signals. The test control unit measures the output V.sub.out of the differential amplifier and computes the value of the test gain. A break in either the signal wire or the return wire will result in a test gain of 1. If the signal and return wires are shorted, the test gain will be 1+R.sub.fb /R.sub.in.
    Type: Grant
    Filed: February 15, 1995
    Date of Patent: July 2, 1996
    Assignee: General Electirc Company
    Inventors: Michael P. Weir, Hunt A. Sutherland