Abstract: A microelectronics package comprising a substrate, the substrate comprising a dielectric and at least first and second conductor level within the dielectric, where the first and second conductor levels are separated by at least one dielectric layer. The microelectronics package comprises an inductor structure that comprises a magnetic core. The magnetic core is at least partially embedded within the dielectric. The inductor structure comprises a first trace in the first conductor level, a second trace in the second conductor level, and a via interconnect connecting the first and second traces. The first trace and the second trace extend at least partially within the magnetic core.

Abstract: Methods and systems for attaching a radiopaque marker to a prosthetic heart valve to indicate a location of a commissure of the prosthetic heart valve are disclosed. As one example, a prosthetic heart valve includes a frame including a plurality of struts forming a plurality of cells of the frame arranged between an inflow end and an outflow end of the frame, a plurality of leaflets arranged within the frame, and at least one commissure comprising an attachment member arranged across a selected cell of the plurality of cells of the frame and commissure tabs of two adjacent leaflets coupled to the attachment member. The valve further includes a radiopaque marker arranged on the attachment member of the commissure within the selected cell.

Abstract: An apparatus is provided which comprises: a plurality of plated through holes; a material with magnetic properties adjacent to the plurality of plated through holes; and one or more conductors orthogonal to a length of the plurality of plated through holes, the one or more conductors to couple one plated through hole of the plurality with another plated through hole of the plurality such that an inductor is formed.

Abstract: A microelectronics package comprising a substrate, the substrate comprising a dielectric and at least first and second conductor level within the dielectric, where the first and second conductor levels are separated by at least one dielectric layer. The microelectronics package comprises an inductor structure that comprises a magnetic core. The magnetic core is at least partially embedded within the dielectric. The inductor structure comprises a first trace in the first conductor level, a second trace in the second conductor level, and a via interconnect connecting the first and second traces. The first trace and the second trace extend at least partially within the magnetic core.

Abstract: A microelectronics package comprises a substrate that comprises a dielectric and at least two conductor layers within the dielectric, and an inductor structure having a magnetic core at least partially within the dielectric and extending at least between a first conductor layer and a second conductor layer. The inductor structure comprises at least one conductor that extends horizontally at least partially within the magnetic core. The conductor extends in the z-direction within the magnetic core between the first conductor layer and the second conductor layer. One or more vias extend within the dielectric adjacent to the magnetic core between the first conductor layer and the second conductor layer. The conductor of the inductor has a length extending through the magnetic core that is greater than a width of the conductor.

Abstract: A microelectronics package comprising a substrate, the substrate comprising a dielectric and at least first and second conductor level within the dielectric, where the first and second conductor levels are separated by at least one dielectric layer. The microelectronics package comprises an inductor structure that comprises a magnetic core. The magnetic core is at least partially embedded within the dielectric. The inductor structure comprises a first trace in the first conductor level, a second trace in the second conductor level, and a via interconnect connecting the first and second traces. The first trace and the second trace extend at least partially within the magnetic core.

Abstract: Embodiments include a microelectronic device package structure having an inductor at least partially embedded within a substrate. At least one thermal solution structure may be on a surface of the inductor, and may be thermally coupled with the inductor. The one or more thermal solution structures provide a thermal pathway for cooling for the inductor, and extend a thermal time constant of the inductor.

Abstract: Embodiments disclosed herein include power transformers for microelectronic devices. In an embodiment, a power transformer comprises a magnetic core that is a closed loop with an inner dimension and an outer dimension, and a primary winding around the magnetic core. In an embodiment, the primary winding has a first number of first turns connected in series around the magnetic core. In an embodiment, a secondary winding is around the magnetic core, and the secondary winding has a second number of second turns around the magnetic core. In an embodiment, individual ones of the second turns comprise a plurality of secondary segments connected in parallel.

Abstract: Embodiments disclosed herein include magnetic structures and methods of forming such structures. In an embodiment, the magnetic structure includes an interconnect. In an embodiment, the interconnect comprises a core, where the core has a thickness and a length between a first end and a second end. In an embodiment, the core is conductive. In an embodiment, the interconnect further comprises a magnetic sheet surrounding the core. In an embodiment, the magnetic sheet comprises is a magnetic layer with a microstructure that comprises grains that are substantially aligned in a single direction.

Abstract: An apparatus is provided which comprises: a plurality of plated through holes; a material with magnetic properties adjacent to the plurality of plated through holes; and one or more conductors orthogonal to a length of the plurality of plated through holes, the one or more conductors to couple one plated through hole of the plurality with another plated through hole of the plurality such that an inductor is formed.

Abstract: A microelectronics package comprises a substrate comprising at least two conductive layers that are separated by a first dielectric. At least one island comprising a magnetic material is embedded within the dielectric between the two conductive layers. An inductor structure extends within a via in the at least one island. The via extends between the two conductive layers. The inductor structure comprises a conductive wall along a sidewall of the via, and wherein the conductive wall surrounds a second dielectric and is electrically coupled to the two conductive layers.

Abstract: A microelectronics package comprises a substrate that comprises a dielectric and at least two conductor layers within the dielectric, and an inductor structure having a magnetic core at least partially within the dielectric and extending at least between a first conductor layer and a second conductor layer. The inductor structure comprises at least one conductor that extends horizontally at least partially within the magnetic core. The conductor extends in the z-direction within the magnetic core between the first conductor layer and the second conductor layer. One or more vias extend within the dielectric adjacent to the magnetic core between the first conductor layer and the second conductor layer. The conductor of the inductor has a length extending through the magnetic core that is greater than a width of the conductor.

Abstract: A microelectronics package comprising a substrate, the substrate comprising a dielectric and at least first and second conductor level within the dielectric, where the first and second conductor levels are separated by at least one dielectric layer. The microelectronics package comprises an inductor structure that comprises a magnetic core. The magnetic core is at least partially embedded within the dielectric. The inductor structure comprises a first trace in the first conductor level, a second trace in the second conductor level, and a via interconnect connecting the first and second traces. The first trace and the second trace extend at least partially within the magnetic core.

Abstract: Embodiments include a microelectronic device package structure having an inductor at least partially embedded within a substrate. At least one thermal solution structure may be on a surface of the inductor, and may be thermally coupled with the inductor. The one or more thermal solution structures provide a thermal pathway for cooling for the inductor, and extend a thermal time constant of the inductor.

Abstract: In general the disclosure relates to manufacturing methods for producing conductive patterns on flexible substrates. For example, a layer of a metal powder composition is deposited onto an adhesive overlaying a substrate. Pressure is applied to the metal powder composition on the adhesive coated substrate web by a die having one or more projections, in order to reproduce a pattern on the substrate. The metal powder is compressed by the projections of the die, thereby densifying the powder and causing it to adhere to the adhesive in a reproduction of the die pattern. The metal powder does not adhere substantially in uncompressed regions, and may be removed. In this manner, a metal powder composition may be densified and adhered to a substrate forming a web of flexible circuit elements, for example, circuit elements such as antennas, resistors, capacitors, inductive coils, conduction pads and the like.

Abstract: The present invention describes a system and method of managing digital content received from content providers and for facilitating access to the digital content to many subscribers. The method includes receiving from the content providers incoming feed files where each feed file contains information describing the content. The method determines if the feed files are approved by applying a template to the feed files and also receives request files from the subscribers where each request file contains search criteria. The method provides one or more answer files in response to the request files where each answer file identifies feed files that meet the search criteria of a corresponding request file. The answer files are used to access or permit access to digital content on the web. In addition, a graphical user interface is described to manage, edit, promote and delete the feed files provided to the system.

Abstract: An organic land grid array having multiple built up layers of metal sandwiching non-conductive layers, having a staggered pattern of degassing holes in the metal layers. The staggered pattern occurs in two substantially perpendicular directions. Traces between the metal layers have reduced impedance variation due to the degassing hole pattern.

Abstract: In a method for providing routing between logic cells, the logic cells are arranged in rows. Intercell connectors within each row of logic cells are aligned, for example in the middle of the rows, to form channel boundaries. The intercell connectors are then channel routed in metal layers above the logic cells. Alternately, intercell connectors are placed within the logic cells, however, these intercell connectors are not necessarily aligned. For each intercell connector which is not on a boundary of a routing channel, a substitute connector is located at the boundary of a routing channel. The substitute connectors and the intercell connectors which are on the boundaries of the routing channels are channel routed. Length of routing segments are then adjusted to substitute connectors to extend to intercell connectors instead of the substitute connectors.

Abstract: A method of routing interconnections of devices in a planar field by the use of a computer. The method effectively shortens the length of all interconnections, including interconnections which connect points on the same device, in accordance with design rules. Also, the layers constituting the planar field can be assigned weights to effectively minimize the appearance of interconnections in the layer having the highest assigned weight.