Abstract: Disclosed are methodology and corresponding device subject matters for providing single layer ceramic capacitors through the use of significantly reduced numbers of processing steps. An aspect of present methodology resides in the early introduction of a plurality of selectively spaced through holes in an unfired ceramic wafer. Such holes provide connection points between conductive coatings on both sides of a subsequently fired wafer and eliminate the need to perform a previously employed third sputtering step to achieve connection between the layers. The present methodology also provides for end of process determination of final capacitive values for the finished devices.

Abstract: A single layer capacitive device and a method of making the same are provided. Such method allows for perfect registration between the capacitive plates thus eliminating any significant amount of fringe capacitance and assuring a uniform fringe border around the device. Such a border ensures ease of handling and such method allows for a controlled border in a range of from about 0.5 mils to about 2.0 mils wide. Further, such a method allows for the manufacture of single layer capacitive arrays comprising numerous individual capacitive devices with similar perfect registration and uniform fringe borders. Such devices allow for improved volumetric efficiencies and reduced fringe capacitance, thus offering higher capacitor values in a smaller package size due to greater control during finishing processes.

Abstract: A single layer capacitive device and a method of making the same are provided. Such method allows for perfect registration between the capacitive plates thus eliminating any significant amount of fringe capacitance and assuring a uniform fringe border around the device. Such a border ensures ease of handling and such method allows for a controlled border in a range of from about 0.5 mils to about 2.0 mils wide. Further, such a method allows for the manufacture of single layer capacitive arrays comprising numerous individual capacitive devices with similar perfect registration and uniform fringe borders. Such devices allow for improved volumetric efficiencies and reduced fringe capacitance, thus offering higher capacitor values in a smaller package size due to greater control during finishing processes.