Patents by Inventor Huong T. Nguyen

Huong T. Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190266036
    Abstract: An information handling system includes a processor, a dual in-line memory module (DIMM), and a memory controller coupled to the DIMM. The memory controller provides interrupts to the processor each time a read transaction from the DIMM results in a correctable read error. The processor instantiates a failure predictor to receive the interrupts, accumulate a count of the interrupts, and provide a first error indication when the count exceeds a first error threshold. The failure predictor increments the count each time the predictor receives a particular interrupt and decrements the count in accordance with an error leak rate. The error leak rate has a first value when the DIMM is newer than a first age threshold and has a second value when the DIMM is older than the first age threshold.
    Type: Application
    Filed: February 23, 2018
    Publication date: August 29, 2019
    Inventors: René Franco, Amit S. Shah, Huong T. Nguyen, Vijay B. Nijhawan, Vadhiraj Sankaranarayanan, Mark L. Farley, Andrew Butcher
  • Publication number: 20190266037
    Abstract: An information handling system includes a processor, a dual in-line memory module (DIMM), and a memory controller coupled to the DIMM. The memory controller provides interrupts to the processor each time a read transaction from the DIMM results in a correctable read error. The processor instantiates a failure predictor that receives the interrupts, accumulates a count of the interrupts, and provides an error indication when the count exceeds an error threshold. The failure predictor receives a first in time interrupt, suspends the accumulation of the count for a first duration of time in response to receiving the first in time interrupt, and resumes the accumulation of the count. In resuming the accumulation of the count, the failure predictor increments the count each time the predictor receives a first subsequent interrupt and decrements the count in accordance with an error leak rate.
    Type: Application
    Filed: February 23, 2018
    Publication date: August 29, 2019
    Inventors: Amit S. Shah, Huong T. Nguyen, James R. Pledge, Vadhiraj Sankaranarayanan
  • Patent number: 7702971
    Abstract: A method of predicting failure of an information handling device, such as a server, by monitoring an error rate, i.e., n errors per error period. Errors are reported only if the error rate is exceeded. An error count is kept, and errors are leaked from the count if the time difference between errors is more than the error period.
    Type: Grant
    Filed: June 6, 2007
    Date of Patent: April 20, 2010
    Assignee: Dell Products L.P.
    Inventors: Tuyet-Huong T. Nguyen, Mukund Khatri
  • Patent number: 7550851
    Abstract: A process is described that forms a low resistivity connection between a tungsten layer and a silicon surface with high adherence of the tungsten to the silicon. The silicon surface is plasma-cleaned to remove native oxide. A very thin layer (one or more monolayers) of Si-NH2 is formed on the silicon surface, serving as an adhesion layer. A WNx layer is formed over the Si-NH2 layer, using an atomic layer deposition (ALD) process, to serve as a barrier layer. A thick tungsten layer is formed over the WNx layer by CVD. An additional metal layer (e.g., aluminum) may be formed over the tungsten layer.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: June 23, 2009
    Assignee: Novellus Systems, Inc.
    Inventors: Huong T. Nguyen, Dennis Hausmann
  • Publication number: 20080307273
    Abstract: A method of predicting failure of an information handling device, such as a server, by monitoring an error rate, i.e., n errors per error period. Errors are reported only if the error rate is exceeded. An error count is kept, and errors are leaked from the count if the time difference between errors is more than the error period.
    Type: Application
    Filed: June 6, 2007
    Publication date: December 11, 2008
    Applicant: DELL PRODUCTS L.P.
    Inventors: Tuyet-Huong T. Nguyen, Mukund Khatri
  • Patent number: 7160802
    Abstract: A process is described that forms a low resistivity connection between a tungsten layer and a silicon surface with high adherence of the tungsten to the silicon. The silicon surface is plasma-cleaned to remove native oxide. A very thin layer (one or more monolayers) of Si—NH2 is formed on the silicon surface, serving as an adhesion layer. A WNx layer is formed over the Si—NH2 layer, using an atomic layer deposition (ALD) process, to serve as a barrier layer. A thick tungsten layer is formed over the WNx layer by CVD. An additional metal layer (e.g., aluminum) may be formed over the tungsten layer.
    Type: Grant
    Filed: June 6, 2005
    Date of Patent: January 9, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Huong T. Nguyen, Dennis Hausmann
  • Patent number: 6991739
    Abstract: A method of photoresist removal is described. A substrate is located in a processing chamber. A mixture of gases is excited, the mixture comprising a majority component of a reducing process gas and a minority component of between 0.1% and 10% by volume of an oxidizing process gas. Reactive gas species are thereby generated. A photoresist layer with an exposed dielectric layer on the substrate in the chamber is then exposed to the reactive gas mixture to selectively remove the photoresist layer from the dielectric layer.
    Type: Grant
    Filed: October 15, 2001
    Date of Patent: January 31, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Mark N. Kawaguchi, Huong T. Nguyen, Nikolaos Bekiaris, James S. Papanu
  • Patent number: 6578099
    Abstract: A computer system and a method for allocating power to hot-plugged adapter cards placed in a card slot so as to delay, the power allocation until a user is clear of the adapter card. The computer system conventionally includes a processor, a card slot in data communication with the processor, a memory in data communication with the processor, and a power supply in electrical communication with the processor. The memory stores computer-readable data that includes code to be operated on by the processor to allocate power to the card slot upon both a detection of a change of state of the card slot and the occurrence of a predefined system event. The predefined system event is typically a system interrupt that is generated in response to an activation of a switch in electrical communication with the processor.
    Type: Grant
    Filed: January 4, 2000
    Date of Patent: June 10, 2003
    Assignee: Dell USA, L.P.
    Inventors: Robert G. Bassman, Tuyet-Huong T. Nguyen, Wai-Ming R. Chan, Prakash Chauhan
  • Publication number: 20030075524
    Abstract: A method of photoresist removal is described. A substrate is located in a processing chamber. A mixture of gases is excited, the mixture comprising a majority component of a reducing process gas and a minority component of between 0.1% and 10% by volume of an oxidizing process gas. Reactive gas species are thereby generated. A photoresist layer with an exposed dielectric layer on the substrate in the chamber is then exposed to the reactive gas mixture to selectively remove the photoresist layer from the dielectric layer.
    Type: Application
    Filed: October 15, 2001
    Publication date: April 24, 2003
    Applicant: Applied Materials, Inc.
    Inventors: Mark N. Kawaguchi, Huong T. Nguyen, Nikolaos Bekiaris, James S. Papanu
  • Publication number: 20020133695
    Abstract: An apparatus and method are disclosed for reducing the amount of time to execute a boot sequence, such as a power-on self-test (POST) routine, by eliminating a scan for devices interfaced with a local bus associated with a computer system. A detection circuit interfaces with a card slot through the local bus and generates a status bit indicating whether the configuration of devices for the computer system changed after completion of a first boot sequence. A processor interfaces with the local bus and reads the status bit during a second boot sequence. If the status bit indicates that the computer system device configuration remains the same, the processor eliminates the scan for devices interfaced with the computer system.
    Type: Application
    Filed: January 25, 2001
    Publication date: September 19, 2002
    Applicant: DELL PRODUCTS L.P.
    Inventors: Mukund P. Khatri, Tuyet-Huong T. Nguyen, Albert J. Bolian
  • Patent number: 6246428
    Abstract: A method of thermal mass transfer printing a colorant including a binder media from a ribbon onto a first surface of a web having a non-homogeneous thermal conductivity, a non-planar printing surface, a non-homogeneous structure or chemical incompatibility. The first surface of the web is preheated prior to thermal mass transfer printing. The surface of the ribbon containing the colorant is positioned opposite the first surface of the heated web at an inner face. A thermal print head is positioned at the interface on the side of the ribbon opposite the colorant. The web is moved relative to the thermal print head. Printing is completed by selectively applying localized heat to the ribbon from the thermal print head and pressure at the interface to cause the transfer of colorant from the ribbon to the heated web.
    Type: Grant
    Filed: May 11, 1999
    Date of Patent: June 12, 2001
    Assignee: 3M Innovoative Properties Company
    Inventors: Thomas F. Look, Michael G. O'Reilly, Thanh-Huong T. Nguyen, Craig A. Schmidt
  • Patent number: 4642346
    Abstract: Novel anhydrous crystalline 9-(1,3-dihydroxy-2-propoxymethyl)guanine useful as an antiviral agent.
    Type: Grant
    Filed: June 24, 1985
    Date of Patent: February 10, 1987
    Assignee: Syntex (U.S.A.) Inc.
    Inventors: Tai W. Chan, Huong T. Nguyen