Patents by Inventor Hup Chin Teh

Hup Chin Teh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Scalable micro bumps indexing and redundancy scheme for homogeneous configurable integrated circuit dies
    Patent number: 11336286
    Abstract: A method includes detecting an open in a first IO element of a first bank of IOs and not in a second bank of IOs. The first and second banks of IOs are in a channel of a first die. The method includes shifting a first connection between the first IO element and a first core fabric of the first die to second connection between a second IO element and the first core fabric. The second IO element is in the first bank of IOs. The method includes shifting a third connection between a third IO element and a second core fabric of a second die to fourth connection between a fourth IO element and the second core fabric. The third and fourth IO elements are in a third bank of IOs of the second die. The method includes not shifting connections in the second and fourth banks of IOs.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Lai Guan Tang, Hup Chin Teh, Kiun Kiet Jong
  • Scalable Micro Bumps Indexing and Redundancy Scheme for Homogeneous Configurable Integrated Circuit Dies
    Publication number: 20190158096
    Abstract: A method includes detecting an open in a first IO element of a first bank of IOs and not in a second bank of IOs. The first and second banks of IOs are in a channel of a first die. The method includes shifting a first connection between the first IO element and a first core fabric of the first die to second connection between a second IO element and the first core fabric. The second IO element is in the first bank of IOs. The method includes shifting a third connection between a third IO element and a second core fabric of a second die to fourth connection between a fourth IO element and the second core fabric. The third and fourth IO elements are in a third bank of IOs of the second die. The method includes not shifting connections in the second and fourth banks of IOs.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 23, 2019
    Applicant: Intel Corporation
    Inventors: Lai Guan Tang, Hup Chin Teh, Kiun Kiet Jong