Patents by Inventor Husam Alshareef
Husam Alshareef has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230197361Abstract: Embodiments include an electrode material including a plurality of cores fused to a plurality of redox active linkers via Aza units to form a layered two-dimensional (2D) Aza-fused pi-conjugated covalent organic framework (COF). Embodiments also include a negative electrode material including the electrode material, as well as a supercapacitor device and an asymmetric supercapacitor device including the electrode material. Embodiments further include a method of making an electrode material including one or more of the following steps: combining a hexaketocyclohexane compound and an aromatic tetraamine compound in a solution; mixing the solution including the hexaketocyclohexane compound and the aromatic tetraamine compound; and heating the mixed solution to form a 2D Aza-fused pi-conjugated COF.Type: ApplicationFiled: June 1, 2021Publication date: June 22, 2023Inventors: Mohamed EDDAOUDI, Jiangtao JIA, Sharath KANDAMBETH, Osama SHEKHAH, Husam ALSHAREEF
-
Patent number: 9976913Abstract: Embodiments of the present disclosure include nanowire field-effect transistors, systems for temperature history detection, methods for thermal history detection, a matrix of field effect transistors, and the like.Type: GrantFiled: November 20, 2014Date of Patent: May 22, 2018Assignee: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGYInventors: Jesus Alfonso Caraveo Frescas, Husam Alshareef
-
Patent number: 9305706Abstract: Disclosed is a fractional order capacitor comprising a dielectric nanocomposite layer of thickness t, comprising a first side, and a second side opposite the first side, a first electrode layer coupled to the first side of the dielectric nanocomposite layer, a second electrode layer coupled to the second side of the dielectric nanocomposite layer, a complex impedance phase angle dependent on at least a material weight percentage of filler material in a dielectric nanocomposite layer.Type: GrantFiled: March 6, 2014Date of Patent: April 5, 2016Assignee: Saudi Basic Industries CorporationInventors: Mahmoud N. Almadhoun, Amro Elshurafa, Khaled Salama, Husam Alshareef
-
Publication number: 20150146761Abstract: Embodiments of the present disclosure include nanowire field-effect transistors, systems for temperature history detection, methods for thermal history detection, a matrix of field effect transistors, and the like.Type: ApplicationFiled: November 20, 2014Publication date: May 28, 2015Inventors: Jesus Alfonso Caraveo Frescas, Husam Alshareef
-
Publication number: 20140266374Abstract: Disclosed is a fractional order capacitor comprising a dielectric nanocomposite layer of thickness t, comprising a first side, and a second side opposite the first side, a first electrode layer coupled to the first side of the dielectric nanocomposite layer, a second electrode layer coupled to the second side of the dielectric nanocomposite layer, a complex impedance phase angle dependent on at least a material weight percentage of filler material in a dielectric nanocomposite layer.Type: ApplicationFiled: March 6, 2014Publication date: September 18, 2014Applicant: SAUDI BASIC INDUSTRIES CORPORATIONInventors: Mahmoud N. Almadhoun, Amro Elshurafa, Khaled Salama, Husam Alshareef
-
Patent number: 8409943Abstract: Semiconductor devices and fabrication methods are provided, in which fully silicided gates are provided. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal. This process and resultant structure provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting transistor.Type: GrantFiled: December 28, 2010Date of Patent: April 2, 2013Assignee: Texas Instruments IncorporatedInventors: Manfred Ramin, Michael F. Pas, Husam Alshareef
-
Patent number: 8304333Abstract: A method for manufacturing a semiconductor device includes forming a gate electrode over a gate dielectric. The gate dielectric is formed by forming a lanthanide metal layer over a nitrided silicon oxide layer, and then performing an anneal to inter-diffuse atoms to form a lanthanide silicon oxynitride layer. A gate electrode layer may be deposited before or after the anneal. In an embodiment, the gate electrode layer includes a non-lanthanide metal layer, a barrier layer formed over the non-lanthanide metal layer, and a polysilicon layer formed over the barrier layer. Hafnium atoms may optionally be implanted into the nitrided silicon oxide layer.Type: GrantFiled: September 21, 2010Date of Patent: November 6, 2012Assignee: Texas Instruments IncorporatedInventors: Manfred Ramin, Michael F. Pas, Husam Alshareef
-
Publication number: 20110223757Abstract: Semiconductor devices and fabrication methods are provided, in which fully silicided gates are provided. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal. This process and resultant structure provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting transistor.Type: ApplicationFiled: December 28, 2010Publication date: September 15, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Manfred Ramin, Michael F. Pas, Husam Alshareef
-
Patent number: 8008216Abstract: Metal Oxide Semiconductor (MOS) transistors fabricated using current art may utilize a nitridation process on the gate dielectric to improve transistor reliability. Nitridation by the current art, which involves exposing the gate dielectric to a nitridation source, produces a significant concentration of nitrogen at the interface of the gate dielectric and the transistor substrate, which adversely affects transistor performance. This invention comprises the process of depositing a sacrificial layer on the gate dielectric prior to nitridation, exposing the sacrificial layer to a nitridation source, during which time nitrogen atoms diffuse through the sacrificial layer into the gate dielectric, then removing the sacrificial layer without degrading the gate dielectric. Work associated with this invention on high-k gate dielectrics has demonstrated a 20 percent reduction in nitrogen concentration at the gate dielectric—transistor substrate interface.Type: GrantFiled: September 24, 2007Date of Patent: August 30, 2011Assignee: Texas Instruments IncorporatedInventors: Husam Alshareef, Manuel Quevedo Lopez
-
Publication number: 20110006375Abstract: A method for manufacturing a semiconductor device includes forming a gate electrode over a gate dielectric. The gate dielectric is formed by forming a lanthanide metal layer over a nitrided silicon oxide layer, and then performing an anneal to inter-diffuse atoms to form a lanthanide silicon oxynitride layer. A gate electrode layer may be deposited before or after the anneal. In an embodiment, the gate electrode layer includes a non-lanthanide metal layer, a barrier layer formed over the non-lanthanide metal layer, and a polysilicon layer formed over the barrier layer. Hafnium atoms may optionally be implanted into the nitrided silicon oxide layer.Type: ApplicationFiled: September 21, 2010Publication date: January 13, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Manfred Ramin, Michael F. Pas, Husam Alshareef
-
Patent number: 7858459Abstract: Semiconductor devices and fabrication methods are provided, in which fully silicided transistor gates are provided for MOS transistors. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal. This process and resultant structure provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting transistor.Type: GrantFiled: April 20, 2007Date of Patent: December 28, 2010Assignee: Texas Instruments IncorporatedInventors: Manfred Ramin, Michael F. Pas, Husam Alshareef
-
Patent number: 7807522Abstract: Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. Metal nitride is formed above a gate dielectric. A lanthaide series metal is implanted into the metal screen layer above the gate dielectric. The lanthaide metal is contained in the screen layer or at the interface between the screen metal layer and the gate dielectric. This process provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting PMOS or NMOS transistors.Type: GrantFiled: January 31, 2007Date of Patent: October 5, 2010Assignee: Texas Instruments IncorporatedInventors: Husam Alshareef, Manfred Ramin, Michael F. Pas
-
Patent number: 7799669Abstract: A method for manufacturing a semiconductor device. The method comprises forming a dielectric layer. Forming the dielectric layer includes depositing a silicon oxide layer on a semiconductor substrate, nitridating the silicon oxide layer to form a nitrided silicon oxide layer and incorporating lanthanide atoms into the nitrided silicon oxide layer to form a lanthanide silicon oxynitride layer.Type: GrantFiled: April 27, 2007Date of Patent: September 21, 2010Assignee: Texas Instruments IncorporatedInventors: Manfred Ramin, Michael F. Pas, Husam Alshareef
-
Publication number: 20090104743Abstract: Metal Oxide Semiconductor (MOS) transistors fabricated using current art may utilize a nitridation process on the gate dielectric to improve transistor reliability. Nitridation by the current art, which involves exposing the gate dielectric to a nitridation source, produces a significant concentration of nitrogen at the interface of the gate dielectric and the transistor substrate, which adversely affects transistor performance. This invention comprises the process of depositing a sacrificial layer on the gate dielectric prior to nitridation, exposing the sacrificial layer to a nitridation source, during which time nitrogen atoms diffuse through the sacrificial layer into the gate dielectric, then removing the sacrificial layer without degrading the gate dielectric. Work associated with this invention on high-k gate dielectrics has demonstrated a 20 percent reduction in nitrogen concentration at the gate dielectric-transistor substrate interface.Type: ApplicationFiled: September 24, 2007Publication date: April 23, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Husam Alshareef, Manuel Quevedo Lopez
-
Publication number: 20090039441Abstract: Devices comprising, and method for fabricating, a MOSFET with a metal gate electrode are disclosed. In one embodiment, the MOSFET includes a first doped region configured to receive current from a current source, a second doped region configured to drain current from the first doped region when an electric field is modified between the first doped region and the second doped region, and a gate electrode configured to modify the electric field. The gate electrode may include a high-k layer, a hafnium-based metal layer formed above the high-k layer, and a polysilicon layer formed above the hafnium-based metal layer. In a further embodiment, the gate electrode further comprises a titanium-based metal layer formed between the hafnium-based metal layer and the polysilicon layer.Type: ApplicationFiled: August 10, 2007Publication date: February 12, 2009Inventors: Hongfa Luna, Kisik Choi, Prashant Majhi, Husam Alshareef, Huang-Chun Wen, Rusty Harris, Byoung Hun Lee
-
Publication number: 20080265336Abstract: A method for manufacturing a semiconductor device. The method comprises forming a dielectric layer. Forming the dielectric layer includes depositing a silicon oxide layer on a semiconductor substrate, nitridating the silicon oxide layer to form a nitrided silicon oxide layer and incorporating lanthanide atoms into the nitrided silicon oxide layer to form a lanthanide silicon oxynitride layer.Type: ApplicationFiled: April 27, 2007Publication date: October 30, 2008Applicant: Texas Instruments IncorporatedInventors: Manfred Ramin, Michael F. Pas, Husam Alshareef
-
Publication number: 20080261368Abstract: Semiconductor devices and fabrication methods are provided, in which fully silicided transistor gates are provided for MOS transistors. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal. This process and resultant structure provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting transistor.Type: ApplicationFiled: April 20, 2007Publication date: October 23, 2008Inventors: Manfred Ramin, Michael F. Pas, Husam Alshareef
-
Publication number: 20080242114Abstract: A method of manufacturing a semiconductor device is provided. In one embodiment, the method provides for the formation, over a substrate, of a dielectric layer having a high dielectric constant. This dielectric layer may be exposed to a nitrogen plasma after which it may be annealed in a hydrogen containing ambient.Type: ApplicationFiled: April 2, 2007Publication date: October 2, 2008Applicant: Texas Instruments IncorporatedInventors: Manuel Quevedo-Lopez, Husam Alshareef
-
Publication number: 20080160736Abstract: Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. Metal nitride is formed above a gate dielectric. A lanthaide series metal is implanted into the metal screen layer above the gate dielectric. The lanthaide metal is contained in the screen layer or at the interface between the screen metal layer and the gate dielectric. This process provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting PMOS or NMOS transistors.Type: ApplicationFiled: January 31, 2007Publication date: July 3, 2008Inventors: Husam Alshareef, Manfred Ramin, Michael F. Pas
-
Publication number: 20080116542Abstract: The present invention provides a gate dielectric having a flat nitrogen profile, a method of manufacture therefor, and a method of manufacturing an integrated circuit including the flat nitrogen profile. In one embodiment, the method of manufacturing the gate dielectric includes forming a gate dielectric layer (410) on a substrate (310), and subjecting the gate dielectric layer (410) to a nitrogen containing plasma process (510), wherein the nitrogen containing plasma process (510) has a ratio of helium to nitrogen of 3:1 or greater.Type: ApplicationFiled: January 24, 2008Publication date: May 22, 2008Applicant: Texas Instruments IncorporatedInventors: Hiroaki Niimi, Husam Alshareef, Rajesh Khamankar, Toan Tran