Abstract: A digitally controlled grounded capacitor multiplier includes: a single capacitor directly connected at one end to an input voltage and at another end to a negative input of an operational amplifier; the operational amplifier including a negative feedback loop; and a digitally controlled current amplifier (DCCA) connected to an output of the operational amplifier. The DCCA digitally controls the digitally controlled grounded capacitor multiplier. The digitally controlled grounded capacitor multiplier comprises only two active devices consisting of the operational amplifier and the DCCA.

Abstract: A system for a first digitally controlled grounded inductor simulation circuit may include an OP-AMP, a digitally controlled current amplifier (DCCA), a voltage buffer, two resistors, and a capacitor. The first digitally controlled grounded inductor simulation circuit allows adjustment of an equivalent inductance value (CR1R2/A) through programming a digitally controlled current gain (A) of the DCCA. A system for a second digitally controlled grounded inductor simulation circuit includes an OP-AMP, a digitally controlled current amplifier (DCCA), a dual output current follower (CF), an active current division network (CDN), two resistors, and a capacitor. The second digitally controlled grounded inductor simulation circuit allows adjustment of an equivalent inductance value (CR1R2/?A) via programming the active CDN and the DCCA.

Abstract: A digitally controlled grounded capacitor multiplier includes: a single capacitor directly connected at one end to an input voltage and at another end to a negative input of an operational amplifier; the operational amplifier including a negative feedback loop; and a digitally controlled current amplifier (DCCA) connected to an output of the operational amplifier. The DCCA digitally controls the digitally controlled grounded capacitor multiplier. The digitally controlled grounded capacitor multiplier comprises only two active devices consisting of the operational amplifier and the DCCA.

Abstract: A square wave oscillator includes a Schmitt Trigger with a first output that outputs a first output current, a capacitor connected to the first output of the Schmitt Trigger, and a resistor that connects the capacitor to an input of the Schmitt Trigger to form a closed-loop negative feedback. The closed-loop negative feedback sustains an oscillation of the square wave oscillator and causes a frequency and an amplitude of the oscillation to be independent of a supply voltage of the Schmitt Trigger.

Abstract: A current-mode Schmitt Trigger includes a plurality of current output stages connected to a common supply voltage that powers the current-mode Schmitt Trigger, a main input on one of the current output stages that receives an input current, and a non-inverting output on a different one of the current output stages that is shorted to the main input to establish a positive closed-loop feedback and supplies a non-inverting output current as the input current. The current-mode Schmitt Trigger includes only active components.

Abstract: A digitally controlled grounded capacitance multiplier circuit system and method is disclosed. The capacitance multiplier (CM) circuit comprises an op-amp, a digitally controlled current amplifier and two resistors in addition to a reference capacitor. The CM circuit is designed using complementary metal-oxide-semiconductor (CMOS) technology. The value of the equivalent capacitance can be adjusted through digitally programming the gain of the current amplifier. The CM circuit provides a significant multiplication factor while using two active devices.

Abstract: An active voltage doubler utilizing a single supply op-amp for energy harvesting system is presented. The active voltage doubler is used for rectification of low power alternating energy sources to achieve both acceptably high power conversion efficiency (PCE) and large rectified DC voltage. The op-amp is self-biased, meaning that no external supply is needed but rather it uses part of the harvested energy for its biasing. Further, the rectified DC voltage is almost twice that of the conventional passive doubler. Power conversion efficiency versus load resistance is plotted and demonstrates that the self-biased active voltage doubler is at least twice as efficient as a conventional passive voltage doubler within the range of 20 to 50 K?. The self-biased active voltage doubler achieves maximum power conversion efficiency (PCE) of 61.7% for a 200 Hz sinusoidal input of 0.8V for a 20 K? load resistor.

Abstract: A multiple-gain transconductance amplifier circuit is presented. It is developed by utilizing programmable gain source-coupling differential pair output stage forming multiple-gain transconductance amplifier outputs. A reconfigurable nth-order filter based on a multi-gain transconductance amplifier where the multi-gain transconductance amplifier includes a linear voltage-to-current converter and a programmable current-folding output stage was implemented. The filter achieves independent programmability while still using a single active device per pole. Further, the proposed multiple-gain transconductance amplifier can be employed to design poly phase filters and transconductance amplifier cell for an amplifier-based low-dropout regulator.

Abstract: A CMOS channel select filter for DVB-H direct-conversion receives based on a transresistance amplifier (TRA) is disclosed. The channel select filter includes a fully differential transresistance amplifier (FDTRA) configured to change an input current at each differential input terminal to a voltage at each differential output terminal based on an impedance at a corresponding differential impedance terminal. The channel select filter also includes two feedback resistors, each having one end connected to a respective differential output terminal of the FDTRA and having another end connected to the node, two first capacitors, each connected between ground and the node, and two second capacitors, each connected between ground and a respective differential impedance terminal.

Abstract: A CMOS channel select filter for DVB-H direct-conversion receives based on a transresistance amplifier (TRA) is disclosed. The channel select filter includes a fully differential transresistance amplifier (FDTRA) configured to change an input current at each differential input terminal to a voltage at each differential output terminal based on an impedance at a corresponding differential impedance terminal. The channel select filter also includes two feedback resistors, each having one end connected to a respective differential output terminal of the FDTRA and having another end connected to the node, two first capacitors, each connected between ground and the node, and two second capacitors, each connected between ground and a respective differential impedance terminal.

Abstract: A CMOS channel select filter for DVB-H direct-conversion receives based on a transresistance amplifier (TRA) is disclosed. The channel select filter includes a fully differential transresistance amplifier (FDTRA) configured to change an input current at each differential input terminal to a voltage at each differential output terminal based on an impedance at a corresponding differential impedance terminal. The channel select filter also includes two feedback resistors, each having one end connected to a respective differential output terminal of the FDTRA and having another end connected to the node, two first capacitors, each connected between ground and the node, and two second capacitors, each connected between ground and a respective differential impedance terminal.

Abstract: The reconfigurable Nth-order filter includes a CCII adopting active current division networks for implementing the proposed filter. This digitally programmable second generation current conveyor leads to wide control of filter coefficients for reconfiguration of the filter. Programmability characteristics are demonstrated through experimental results obtained from integrated circuit chips fabricated in a 0.18 ?m CMOS process.

Abstract: The optimal low power complex filter, as a second order complex filter, is based on current amplifiers (CAs) and is utilized to implement a 4th order current-mode filter that can be used for intermediate frequency (IF) applications, such as, for example, low-IF Bluetooth receivers. Fabricated in a standard 0.18 ?m CMOS technology, experimental results show that the present design offers improved characteristics over the existing solutions in terms of power consumption and spurious-free dynamic range (SFDR). The 4th order filter exhibits in-band SFDR of 65.8 dB while consuming only 1 mW.

Abstract: The reconfigurable Nth-order filter includes a CCII adopting active current division networks for implementing the proposed filter. This digitally programmable second generation current conveyor leads to wide control of filter coefficients for reconfiguration of the filter. Programmability characteristics are demonstrated through experimental results obtained from integrated circuit chips fabricated in a 0.18 ?m CMOS process.

Abstract: The fully integrated DC offset compensation servo feedback loop is an integrator that measures the output signal DC component, and then feeds back and subtracts the measured DC component from the input signal. A larger integrator time constant lowers the high pass corner frequency, which must be very small in order to minimize the loss of the low frequency component of the desired signals. The large time constant is achieved on an integrated circuit by the use of a class-AB fully differential opamp in conjunction with an R-2R ladder as a circuit element to accomplish an integrated large time constant integrator. The R-2R ladder is configured as a digitally programmable resistor.

Abstract: The programmable multi-gain current amplifier circuitry includes a pair of MOS transistors setting the voltage at X terminal to zero using negative feedback formed by a third MOS transistor. Input resistance is in the range of few tens of ohms. The input current ix, which is forced by the constant currents of the circuitry, is conveyed to the output port Z by source-coupling a complementary output pair of MOS transistors. Since this coupled pair is biased with a constant tail current, the drain current changes are equal but with opposite sign, regardless of their matching resulting in negative type CA with unity gain (iz=ix). Programmability is achieved utilizing the output stages. When a second differential pair is connected in parallel, it provides two additional current outputs. With the two differential pairs being biased with different tail currents (IT1 and IT2), the outputs are programmed by adjusting these tail currents.

Abstract: The programmable multi-gain current amplifier circuitry includes a pair of MOS transistors setting the voltage at X terminal to zero using negative feedback formed by a third MOS transistor. Input resistance is in the range of few tens of ohms. The input current ix, which is forced by the constant currents of the circuitry, is conveyed to the output port Z by source-coupling a complementary output pair of MOS transistors. Since this coupled pair is biased with a constant tail current, the drain current changes are equal but with opposite sign, regardless of their matching resulting in negative type CA with unity gain (iz=ix). Programmability is achieved utilizing the output stages. When a second differential pair is connected in parallel, it provides two additional current outputs. With the two differential pairs being biased with different tail currents (IT1 and IT2), the outputs are programmed by adjusting these tail currents.

Abstract: The optimal low power complex filter, as a second order complex filter, is based on current amplifiers (CAs) and is utilized to implement a 4th order current-mode filter that can be used for intermediate frequency (IF) applications, such as, for example, low-IF Bluetooth receivers. Fabricated in a standard 0.18 ?m CMOS technology, experimental results show that the present design offers improved characteristics over the existing solutions in terms of power consumption and spurious-free dynamic range (SFDR). The 4th order filter exhibits in-band SFDR of 65.8 dB while consuming only 1 mW.

Abstract: Voltage and current mode reconfigurable nth-order filters (RNOFs), fabricated in a 0.18 ?m CMOS process, utilize an inverse-follow-the-leader-feedback (IFLF) signal path with summed outputs, resulting in a follow-the-leader-feedback-summed-outputs (FLF-SO) filter topology. The FLF-SO filter uses multi-output current amplifiers (CAs). Inverse-follow-the-leader-feedback-summed-outputs (IFLF-SO) and inverse-follow-the-leader-feedback-distributed-outputs (IFLF-DI) structures are realized by employing 3n+4 transconductance amplifiers (TCAs) for voltage mode processing and two TCAs for current mode signals. A plurality of programmable current division networks (CDNs) tune a digitally controlled current follower (DCCF). A multi-output Digitally Controlled Current Amplifier (MDCCA) controls gain by providing independent filter coefficient control. Forward path output gains are set to unity. Alternatively, a multi-output digitally controlled CCII block (MDCCCII) uses CCII in the first stage.

Abstract: Voltage and current mode reconfigurable nth-order filters (RNOFs) fabricated in a 0.18 ?m CMOS process are disclosed. The RNOFs utilize an inverse-follow-the-leader-feedback (IFLF) signal path with summed outputs, resulting in a follow-the-leader-feedback-summed-outputs (FLF-SO) filter topology. The FLF-SO filter uses multi-output current amplifiers (CAs). Inverse-follow-the-leader-feedback-summed-outputs (IFLF-SO) and inverse-follow-the-leader-feedback-distributed-outputs (IFLF-DI) structures are realized by employing 3n+4 transconductance amplifiers (TCAs) for voltage mode processing and two TCAs for current mode signals. A plurality of programmable current division networks (CDNs) tune a digitally controlled current follower (DCCF). A multi-output Digitally Controlled Current Amplifier (MDCCA) controls gain by providing independent filter coefficient control. Forward path output gains are set to unity. Alternatively, a multi-output digitally controlled CCII block (MDCCCII) uses CCII in the first stage.