Abstract: Apparatuses and systems implementing an amplifier module are described. The amplifier module can include a substrate. A driver amplifier die, a splitter network, an output amplifier die, a bias controller, and a combiner network can be coupled to the substrate. The driver amplifier die can be configured to receive an input radio frequency (RF) signal. The splitter network can be configured to split an intermediate RF signal outputted from the driver amplifier die into first and second RF signals. The output amplifier die can be configured to receive the first and second RF signals. The bias controller can be configured to bias the driver amplifier die and the output amplifier die. The combiner network can be configured to combine first and second outputs of the output amplifier die to generate an output RF signal and terminate at least one harmonic of the output amplifier die's output impedance.

Abstract: Systems and methods for amplifying a signal is described. A circuit may convert an input radio frequency (RF) signal into a first RF signal with power level matching a power capacity of a first transistor of a first size in a carrier amplifier stage, a second RF signal with power level matching a power capacity of a second transistor of the first size in a peaking amplifier stage, and a third RF signal with third power level matching a power capacity of a third transistor of a second size in another peaking amplifier stage. The circuit may amplify the first, second, and third RF signals to generate first, second, and third amplified RF signals, respectively. The circuit may combine the first, second, and third amplified RF signals, into an output RF signal that is an amplified version of the input RF signal.

Abstract: A power splitter for use in an amplifier (e.g., a Doherty amplifier) includes an input terminal, and first and second output terminals. The input terminal is configured to receive an input RF signal, the first output terminal is configured to produce a first RF output signal, and the second output terminal is configured to produce a second RF output signal. The power splitter also includes a first capacitance electrically coupled between the input terminal and the first output terminal, a second capacitance electrically coupled between the input terminal and the second output terminal, a first inductance electrically coupled between the input terminal and a ground reference node, a second inductance electrically coupled between the first output terminal and the ground reference node, a third inductance electrically coupled between the second output terminal and the ground reference node, and a resistance electrically coupled between the first and second output terminals.

Abstract: A multiple-path amplifier (e.g., a Doherty amplifier) includes first and second amplifier input terminals and an amplifier output terminal integrally-formed with a semiconductor die, and at least two amplifier cells positioned adjacent to each other between the amplifier input terminals and the amplifier output terminal. Each amplifier cell includes first and second transistors (e.g., field effect transistors) integrally-formed with the semiconductor die, where the first and second transistors each include a transistor input (e.g., a gate terminal) and a transistor output (e.g., a drain terminal). The first transistor input is coupled to the first amplifier input terminal, and the second transistor input is coupled to the second amplifier input terminal. A combining node is coupled to the second transistor output and to the amplifier output terminal, and a first phase shift element (e.g., an inductor) is electrically connected between the first transistor output and the combining node.

Abstract: A power splitter for use in an amplifier (e.g., a Doherty amplifier) includes an input terminal, and first and second output terminals. The input terminal is configured to receive an input RF signal, the first output terminal is configured to produce a first RF output signal, and the second output terminal is configured to produce a second RF output signal. The power splitter also includes a first capacitance electrically coupled between the input terminal and the first output terminal, a second capacitance electrically coupled between the input terminal and the second output terminal, a first inductance electrically coupled between the input terminal and a ground reference node, a second inductance electrically coupled between the first output terminal and the ground reference node, a third inductance electrically coupled between the second output terminal and the ground reference node, and a resistance electrically coupled between the first and second output terminals.

Abstract: A multiple-path amplifier (e.g., a Doherty amplifier) includes first and second amplifier input terminals and an amplifier output terminal integrally-formed with a semiconductor die, and at least two amplifier cells positioned adjacent to each other between the amplifier input terminals and the amplifier output terminal. Each amplifier cell includes first and second transistors (e.g., field effect transistors) integrally-formed with the semiconductor die, where the first and second transistors each include a transistor input (e.g., a gate terminal) and a transistor output (e.g., a drain terminal). The first transistor input is coupled to the first amplifier input terminal, and the second transistor input is coupled to the second amplifier input terminal. A combining node is coupled to the second transistor output and to the amplifier output terminal, and a first phase shift element (e.g., an inductor) is electrically connected between the first transistor output and the combining node.

Abstract: A feed structure for an electrical component includes a slot structure with first and second longitudinal sections opposing one another and first and second interconnect segments opposing one another. The first and second interconnect segments couple the first longitudinal section with the second longitudinal section to form an opening extending through the slot structure, the opening being surrounded by the first longitudinal section, the first interconnect segment, the second longitudinal section, and the second interconnect segment. A first feed node is electrically connected to the slot structure at an intermediate region between first and second ends of the first longitudinal section, and second feed nodes are electrically coupled to the slot structure along the second longitudinal section. In a device or module, the second feed nodes are configured for electrical connection to the electrical component.

Abstract: A feed structure for an electrical component includes a slot structure with first and second longitudinal sections opposing one another and first and second interconnect segments opposing one another. The first and second interconnect segments couple the first longitudinal section with the second longitudinal section to form an opening extending through the slot structure, the opening being surrounded by the first longitudinal section, the first interconnect segment, the second longitudinal section, and the second interconnect segment. A first feed node is electrically connected to the slot structure at an intermediate region between first and second ends of the first longitudinal section, and second feed nodes are electrically coupled to the slot structure along the second longitudinal section. In a device or module, the second feed nodes are configured for electrical connection to the electrical component.

Abstract: A radio frequency (RF) chip capacitor circuit and structure are provided. The circuit and structure include a plurality of capacitors connected in series. Each capacitor of the plurality includes a first plate formed from a first metal layer and a second plate formed from a second metal layer. A first two adjacent capacitors of the plurality include first plates formed in a first contiguous portion of the first metal layer or second plates formed in a second contiguous portion of the second metal layer. Each capacitor of the plurality may include a dielectric layer disposed between the first plate and the second plate.

Abstract: An integrated circuit (IC) includes an input pad and an output pad separated from the input pad by a predetermined distance. A plurality of capacitors are coupled in series between the input pad and the output pad. The plurality of capacitors are distributed to substantially span the predetermined distance. An inductor is formed from a bond wire, having a first end attached at the first input pad and a second end attached at the output pad. The inductor and plurality of capacitors configured to form a predetermined open circuit resonance.

Abstract: A radio frequency (RF) chip capacitor circuit and structure are provided. The circuit and structure include a plurality of capacitors connected in series. Each capacitor of the plurality includes a first plate formed from a first metal layer and a second plate formed from a second metal layer. A first two adjacent capacitors of the plurality include first plates formed in a first contiguous portion of the first metal layer or second plates formed in a second contiguous portion of the second metal layer. Each capacitor of the plurality may include a dielectric layer disposed between the first plate and the second plate.

Abstract: An integrated circuit (IC) includes an input pad and an output pad separated from the input pad by a predetermined distance. A plurality of capacitors are coupled in series between the input pad and the output pad. The plurality of capacitors are distributed to substantially span the predetermined distance. An inductor is formed from a bond wire, having a first end attached at the first input pad and a second end attached at the output pad. The inductor and plurality of capacitors configured to form a predetermined open circuit resonance.