Abstract: Data transformer apparatus comprising a dispatcher module, a reader module, a converter module and a writer module; the dispatcher module is configured to receive a data transformation request including a first and a second information items; the reader module is configured to retrieve data to be transformed, according to said first information item; obtain the type attribute of the data to be transformed, based on said first information item; send the data to be transformed and the type attribute to the converter module; the converter module is configured to select transformation instructions based on said type attribute; execute, on the data to be transformed, the selected transformation instructions, thereby obtaining transformed data; send the transformed data to the writer module; the writer module is configured to; write the transformed data in an output buffer according to said second information item.

Abstract: A system for controlling a quantum processor comprises a controller device having a plurality of input channels and output channels connected to qubit readout instruments and qubit control instruments . The controller device forms a register bank for receiving the data from the input channels , a feedback block for processing the data from the register bank , and an output interface for sending the results of the feedback block to the control instruments . For each input channel , the controller device comprises a mask generator with its own address decoder for processing the update messages on the input channels in parallel. Each update message comprises address data , data values for several registers and validity bits indicating if the data values are valid.

Abstract: A system for controlling a quantum processor includes a system controller having a plurality of input channels and output channels connected to qubit readout instruments and qubit control instruments. The system controller is implemented at least in part as an FPGA. It forms a register bank for receiving the data from the input channels, a feedback block for processing the data from the register bank, and an output interface for sending the results of the feedback block to the control instruments. The feedback block can be programmed by an FPGA configuration device. The FPGA configuration device is able to process various types of feedback block definitions, which e.g. describe lookup tables, minimizers, Boolean operations, etc. A configuration device includes a system compiler agnostic of the specific implementation of the feedback block for controlling the experiments and the operation of the instruments.

Abstract: Data transformer apparatus comprising at least a dispatcher module (D), a reader module (R), a converter module (C) and a writer module (W). The dispatcher module (D) is configured to: receive a data transformation request (DTR) including: a first information item (X1) associated to a memory address where data to be transformed (Data1) are stored and to a type attribute (T) of said data to be transformed (Data1); a second information item (X2) indicating a memory address where transformed data (Data2), obtained from said data to be transformed (Data1), have to be written. The reader module (R) is configured to: retrieve the data to be transformed, according to said first information item (X1); obtain the type attribute (T) of the data to be transformed (Data1), based on said first information item (X1); send the data to be transformed (Data1) and the type attribute (T) thereof to the converter module (C).