Abstract: A bus-based apparatus and method for synchronous priority arbitration between modules in a computer system. The modules in the system have priority codes selected from the set B(m,r) of bounded weight codes. Arbitration is completed in, at most, r units of time. The design of the system can be optimized for speed, logic per module, and/or the number of modules connected to any bus line. Both arbitration time and arbitration logic may be decreased by increasing the bus width. The number of modules can be increased indefinitely by increasing only bus-width, while keeping arbitration time and arbitration logic fixed. The arbitration bus is a wired-OR bus.