Patents by Inventor Huw Francis

Huw Francis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9563500
    Abstract: A sequence code verification system can be designed to include a data reader, a validity engine, and an error notifier. The data reader can read sequence codes from consecutive logical blocks. The validity engine can invalidate write operations in response to checking data validity by applying comparison operations to sequence codes and block offsets of batch write operations. The error notifier can notify a user of an error for each invalidated write operation batch. The system can validate data written to logical blocks on a storage subsystem adapted so that, during write operations, an additional sequence code is written to each logical block of data. The sequence code can remain constant for each write operation batch and the sequence code can be incremented for each new write operation batch.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: February 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Huw Francis, David A. Sinclair
  • Publication number: 20160196178
    Abstract: This disclosure relates to validating data written to logical blocks on a storage subsystem adapted so that during write operations an additional sequence code is written to each logical block of data, where the sequence code remains constant for each write operation batch and where the sequence code is incremented for each new write operation batch. A sequence code verification system may comprise a data reader, a validity engine, and an error notifier. The data reader may read sequence codes from consecutive logical blocks. The validity engine may invalidate write operations in response to checking data validity by applying comparison operations to sequence codes and block offsets of batch write operations. The error notifier may notify a user of an error for each invalidated write operation batch.
    Type: Application
    Filed: March 14, 2016
    Publication date: July 7, 2016
    Inventors: Huw Francis, David A. Sinclair
  • Patent number: 9304845
    Abstract: A sequence code verification system can be designed to include a data reader, a validity engine, and an error notifier. The data reader can read sequence codes from consecutive logical blocks. The validity engine can invalidate write operations in response to checking data validity by applying comparison operations to sequence codes and block offsets of batch write operations. The error notifier can notify a user of an error for each invalidated write operation batch. The system can validate data written to logical blocks on a storage subsystem adapted so that, during write operations, an additional sequence code is written to each logical block of data. The sequence code can remain constant for each write operation batch and the sequence code can be incremented for each new write operation batch.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: April 5, 2016
    Assignee: International Business Machines Corporation
    Inventors: Huw Francis, David A. Sinclair
  • Publication number: 20140359399
    Abstract: This disclosure relates to validating data written to logical blocks on a storage subsystem adapted so that during write operations an additional sequence code is written to each logical block of data, where the sequence code remains constant for each write operation batch and where the sequence code is incremented for each new write operation batch. A sequence code verification system may comprise a data reader, a validity engine, and an error notifier. The data reader may read sequence codes from consecutive logical blocks. The validity engine may invalidate write operations in response to checking data validity by applying comparison operations to sequence codes and block offsets of batch write operations. The error notifier may notify a user of an error for each invalidated write operation batch.
    Type: Application
    Filed: April 22, 2014
    Publication date: December 4, 2014
    Applicant: International Business Machines Corporation
    Inventors: Huw Francis, David A. Sinclair
  • Patent number: 7877561
    Abstract: The present invention relates to methods of copying and updating data in a processor memory during program run-time without suspending the program's access to its data in the memory during the data-copying and updating processes. In one aspect, the invention concerns a method of copying data from processor memory to a dump memory during run-time, including determining whether data in a segment of the processor memory is to be updated by a program and copying the data to a corresponding segment in the dump memory prior to the data being updated. According to one embodiment, a data-copying instance is utilized to obtain a point-in-time image of a data content of processor memory while the program is running.
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: January 25, 2011
    Assignee: International Business Machines Corporation
    Inventors: Huw Francis, Colin R. Jewell, Simon Walsh
  • Patent number: 7730370
    Abstract: An apparatus and method for controlling a disk drive is provided. A disk lubricant sweep component for periodically initiates a disk lubricant spreading action. A disk data read check component checks data at one or more LBAs during the disk lubricant sweep. The apparatus may cache data from LBAs that have been checked by the disk data read check component and found correct and record LBAs that have been found correct, so that they can be omitted from subsequent operation of the read check component. The apparatus may further comprise an error checking and correcting component for checking and correcting data found incorrect by reason of a soft error, and an error reporting component for reporting on one or more LBAs that have been checked and found incorrect by reason of a hard error.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: June 1, 2010
    Assignee: International Business Machines Corporation
    Inventors: Huw Francis, Timothy Finbarr McCarthy, Jonathan Ian Settle
  • Publication number: 20090100302
    Abstract: An apparatus and method for controlling a disk drive is provided. A disk lubricant sweep component for periodically initiates a disk lubricant spreading action. A disk data read check component checks data at one or more LBAs during the disk lubricant sweep. The apparatus may cache data from LBAs that have been checked by the disk data read check component and found correct and record LBAs that have been found correct, so that they can be omitted from subsequent operation of the read check component. The apparatus may further comprise an error checking and correcting component for checking and correcting data found incorrect by reason of a soft error, and an error reporting component for reporting on one or more LBAs that have been checked and found incorrect by reason of a hard error.
    Type: Application
    Filed: October 12, 2007
    Publication date: April 16, 2009
    Inventors: Huw Francis, Timothy Finharr McCarthy, Jonathan Ian Settle
  • Publication number: 20080025126
    Abstract: A storage adapter for use in a data storage subsystem includes a controlling processor, a volatile memory, and a nonvolatile memory “dump device.” The storage adapter also includes a battery that can be used to provide sufficient power to the storage adapter to allow data from the volatile memory to be written to the nonvolatile memory of the storage adapter under the control of the processor in the event of an interruption or failure in the main power supply to the storage adapter, i.e. to preserve data stored in the volatile memory in that event. The processor uses the current state of charge of the battery to determine the amount of data that can be “dumped” to the nonvolatile dump device before the battery is depleted.
    Type: Application
    Filed: October 5, 2007
    Publication date: January 31, 2008
    Inventors: Colin Jewell, Robert Nicholson, Huw Francis, David Lee
  • Patent number: 7117320
    Abstract: A method for maintaining data access during failure of a controller in a multiple controller storage subsystem (103) is provided. The storage subsystem (103) has an array of data storage devices (109) and more than one controller (104, 105) for managing the data storage. The method comprises a first controller (201) saving its internal state information (212) and, optionally, resetting itself (213). One or more of the other controllers (202, 203) carry out the steps of pausing operation of the controller (221, 231), saving internal state information of the controller at the time of pausing (222, 232), and continuing operation of the controller (223, 233). The one or more other controllers (202, 203) may pause operation and save their internal state information when they receive a message broadcast (220, 230) from the first controller (201) which has detected an error.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: October 3, 2006
    Assignee: International Business Machines Corporation
    Inventors: Paul Ashmore, Matthew John Fairhurst, Michael Huw Francis, Robert Bruce Nicholson, Simon Walsh, Barry John Wood
  • Patent number: 7080208
    Abstract: A method for data retention in a data cache and a data storage system are provided. The data storage system (100) includes a storage controller (102) with a cache (103) and a data storage means (106). The cache (103) has a first least recently used list (104) for referencing dirty data which is stored in the cache (103), and a second least recently used list (105) for clean data in the cache (103). Dirty data is destaged from the cache (103) when it reaches the tail of the first least recently used list (104) and clean data is purged from the cache (103) when it reaches the tail of the second least recently used list (105).
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: July 18, 2006
    Assignee: International Business Machines Corporation
    Inventors: Paul Ashmore, Michael Huw Francis, Robert Bruce Nicholson, Simon Walsh
  • Publication number: 20050228960
    Abstract: The present invention relates to methods of copying and updating data in a processor memory during program run-time without suspending the program's access to its data in the memory during the data-copying and updating processes. In one aspect, the invention concerns a method of copying data from processor memory to a dump memory during run-time, including determining whether data in a segment of the processor memory is to be updated by a program and copying the data to a corresponding segment in the dump memory prior to the data being updated. According to one embodiment, a data-copying instance is utilized to obtain a point-in-time image of a data content of processor memory while the program is running.
    Type: Application
    Filed: March 28, 2005
    Publication date: October 13, 2005
    Applicant: International Business Machines Corporation
    Inventors: Huw Francis, Colin Jewell, Simon Walsh
  • Publication number: 20050117418
    Abstract: storage adapter for use in a data storage subsystem includes a controlling processor, a volatile memory, and a nonvolatile memory “dump device.” The storage adapter also includes a battery that can be used to provide sufficient power to the storage adapter to allow data from the volatile memory to be written to the nonvolatile memory of the storage adapter under the control of the processor in the event of an interruption or failure in the main power supply to the storage adapter, i.e. to preserve data stored in the volatile memory in that event. The processor uses the current state of charge of the battery to determine the amount of data that can be “dumped” to the nonvolatile dump device using the battery in its current state. The processor then uses that determined amount of data to control the storage of data in the volatile memory.
    Type: Application
    Filed: August 30, 2004
    Publication date: June 2, 2005
    Applicant: International Business Machines Corp.
    Inventors: Colin Jewell, Robert Nicholson, Huw Francis, David Lee
  • Patent number: 6766414
    Abstract: The invention relates to caching data in a data processing system including a host computer and a storage subsystem including at least one customer disk and a cache disk. Write transactions are received specifying data to be written to at least one customer disk and these are cached in a volatile memory of the storage subsystem and written to the cache disk. The transaction data is written sequentially to the cache disk when available. In the intervening periods (i.e., when no transaction data is available), padding data is instead written sequentially to the cache disk.
    Type: Grant
    Filed: May 3, 2001
    Date of Patent: July 20, 2004
    Assignee: International Business Machines Corporation
    Inventors: Michael Huw Francis, Simon Walsh
  • Publication number: 20040049638
    Abstract: A method for data retention in a data cache and a data storage system are provided. The data storage system (100) includes a storage controller (102) with a cache (103) and a data storage means (106). The cache (103) has a first least recently used list (104) for referencing dirty data which is stored in the cache (103), and a second least recently used list (105) for clean data in the cache (103). Dirty data is destaged from the cache (103) when it reaches the tail of the first least recently used list (104) and clean data is purged from the cache (103) when it reaches the tail of the second least recently used list (105).
    Type: Application
    Filed: August 6, 2003
    Publication date: March 11, 2004
    Applicant: International Business Machines Corporation
    Inventors: Paul Ashmore, Michael Huw Francis, Robert Bruce Nicholson, Simon Walsh
  • Publication number: 20040049710
    Abstract: A method for maintaining data access during failure of a controller in a multiple controller storage subsystem (103) is provided. The storage subsystem (103) has an array of data storage devices (109) and more than one controller (104, 105) for managing the data storage. The method comprises a first controller (201) saving its internal state information (212) and, optionally, resetting itself (213). One or more of the other controllers (202, 203) carry out the steps of pausing operation of the controller (221, 231), saving internal state information of the controller at the time of pausing (222, 232), and continuing operation of the controller (223, 233). The one or more other controllers (202, 203) may pause operation and save their internal state information when they receive a message broadcast (220, 230) from the first controller (201) which has detected an error.
    Type: Application
    Filed: June 26, 2003
    Publication date: March 11, 2004
    Applicant: International Business Machines Corporation
    Inventors: Paul Ashmore, John Matthew Fairhurst, Michael Huw Francis, Robert Bruce Nicholson, Simon Walsh, Barry John Wood
  • Publication number: 20030200394
    Abstract: An arrangement and methods for operation in a cache memory system to facitate re-synchronising non-volatile cache memories (150B, 160B) following interruption in communication. A primary adapter (150) creates a non-volatile record (150C) of each cache update before it is applied to either cache. Each such record is cleared when the primary adapter knows that the cache update has been applied to both adapters' caches. In the event of a reset or other failure, the primary adapter can read the non-volatile list of transfers which were ongoing. For each entry in this list, the primary adapter negotiates with the secondary adapter (160) and transfers only the data which may be different.
    Type: Application
    Filed: April 3, 2003
    Publication date: October 23, 2003
    Applicant: International Business Machines Corporation
    Inventors: Paul Ashmore, Michael Huw Francis, Simon Walsh
  • Publication number: 20020004885
    Abstract: The invention relates to caching data in a data processing system including a host computer and a storage subsystem including at least one customer disk and a cache disk. Write transactions are received specifying data to be written to at least one customer disk and these are cached in a volatile memory of the storage subsystem and written to the cache disk. The transaction data is written sequentially to the cache disk when available. In the intervening periods (i.e., when no transaction data is available), padding data is instead written sequentially to the cache disk.
    Type: Application
    Filed: May 3, 2001
    Publication date: January 10, 2002
    Inventors: Michael Huw Francis, Simon Walsh