Abstract: A halftone spot function, for determining a shape of a halftone spot as a function of the intensity of an image being printed, is generated by creating one or two line segments forming a part of the shape of the spot function or by creating a number of contour lines that are interpolated to form the function. A halftone spot pattern is generated as a number of supercells, each of which includes a number of halftone spots, each defined within a halftone spot cell by a halftone spot function, with the supercell being defined to include a number of device pixels, each of which is fully inked of left without ink, a number of spot cells in each direction, and offset distance establishing angles of the lines dividing the spot cells from one another.

Abstract: A logic analyzer is provided with probes (20) deriving the signals to be tested which are introduced into a digitizer (22) provided with comparators which carry out a digitization according to a logic system having two states. It comprises a change-over circuit (21) arranged between the probe and the digitizer, which permits associating several or all comparators with a given signal to be tested to extend its digitization to a multi-level logic system. The change-over circuit (21) is constituted by a matrix of MOS transfer gates or field effect transistors (FET's). When the multi-level logic system has at least one medium state limited by two references, the medium state is displayed on a display device (24) according to a straight line or a monotonic curve joining the two references between the beginning and the end of the medium state. When the duration of the medium state exceeds a predetermined duration, the display device (24) is switched on to display the medium state.

Abstract: A logic analyzer for plural input channels generates trigger signals for first and second triggering modes selected by a multiplexer. In the first mode, a channel selector produces a detection signal in the form of a pulse when the plural input channels simultaneously have logic states matching a reference combination input to the channel selector. In the second mode, the channel selector produces a detection signal in the form of a pulse corresponding to the logic state of a channel selected by a channel selection signal input to the channel selector. The first mode triggering signal exhibits a digital transition when the pulse endures at least as long as a target time period determined by a target count times the interval between clock pulses while the second mode trigger signal exhibits a digital transition when the pulse terminates before enduring for the target time period.