Abstract: A multiplier (42) forms a product from two signed operands without performing a sign extension of the multiplicand (A). A modified Booth's recoding of the multiplier operand (B) is begun immediately without being delayed by a sign extension operation. While recoding and partial product generation is occurring, a determination is made in parallel whether or not a sign extension adjustment term must be created. When needed, a value equal to N (−B) (2N), where N is equal to a bit width of the multiplicand (A), is formed in parallel with the recoding and partial product generation. The sign extension adjustment term is coupled to a plurality of carry save adders (49, 51, 53) that compress a plurality of partial products to a sum term and a carry term. A final add stage combines the sum term and carry term to provide a product with correct sign extension.

Abstract: A circuit and method for level-shifting an input signal are disclosed that provide for level-shifting of a the input signal where an external voltage level is greater than an internal voltage of the signal. In the present invention, the input signal is compared to a reference signal to produce a differential current signal reflecting the logic level of the input signal. The differential current signal is reflected through a pair of current mirrors operating from the external voltage level to drive a pair of resistive loads. Each of the resistive loads is coupled in series with a current sink between the internal supply voltage and a ground voltage. As a result, the input signal may be received and level-shifted with gain even when the internal supply voltage is less than twice a transistor threshold voltage without introducing significant distortion to the received signal.

Abstract: A computer-implemented task workflow management system is provided in which the workflow engines, the program execution means, the process execution rule and the business flow rules are external to the rule evaluator. The invention relates generally to task workflow management systems. More particularly, the present invention relates to a workflow management system which can generate dynamically and iteratively program commands to execute external tools and workflow systems, and can vary task execution sequences dynamically by applying rules to generate next goal or next activity at run time. Business process solutions can be updated automatically and dynamically in response to changes, additions or deletions in any one environment, applications program, and/or change to business data as results of prior implementation of the business solutions. The execution sequences can be dynamically and iteratively updated in response to changes as a result of prior implementation of the business solutions.

Abstract: One embodiment in accordance with the present invention includes a nested flip cover lid for a portable computing system such as a personal digital assistant (PDA). Specifically, the nested flip cover lid includes an accessory rail spine, a hinge and a rigid material that is fabricated to nest within the top cover parameter bevels surrounding the display device of the portable computing system. Therefore, the nested flip cover of the portable computing system is designed and fabricated in order to add a minimal amount of thickness (e.g., 1 millimeter) to the overall portable computing system package. Furthermore, the nested flip cover may also be integrated with a latching mechanism in order to secure the nested flip cover closed when the portable computing system is not being used. In this manner, the latching mechanism keeps the nested flip cover aligned with the outer parameter of the portable computing system.

Abstract: A RAM module that can increase the number of times it may be accessed within a single clock cycle. By knowing the processor's clock speed and determining a critical time, a signal optimizer may be constructed. The critical time is the longest interval of time required for a worst-case scenario memory access. A signal optimizer transforms the clock signal into a signal that has a higher frequency than the original clock signal and maintains both its high state and its low state for at least the critical time. By then allowing the RAM module to perform its access and pre-charge during the dips and posts of the optimized clock signal, the RAM module can perform multiple accesses and pre-charges during one clock cycle. The RAM module can be used for direct memory accesses such that the processor does not need to arbitrate access to the memory.

Abstract: A circuit for discriminating between complementary first and second input signals. By using a logic gate in parallel with a signal amplifying circuit, the signal amplifying circuit can be disabled when it is no longer required. Once the logic gate is capable of detecting distinct complementary states in the two input signals, the signal amplifying circuit is disabled and the circuit uses one of the input signals as its output signal. The circuit is improved by using a pair of Schmitt inverters so the logic circuit will not vacillate unpredictably when the input signals are in an indeterminate state.

Abstract: A synchronous SRAM chip that can increase the number of times it may be accessed within a single clock cycle. By knowing the processor's clock speed and determining a critical time, a signal optimizer may be constructed. The critical time is the longest interval of time required for a worst-case scenario memory access. A signal optimizer transforms the clock signal into a signal that has a higher frequency than the original clock signal and maintains both its high state and its low state for at least the critical time. By then allowing the synchronous SRAM chip to perform its access and pre-charge during the dips and posts of the optimized clock signal, the synchronous SRAM chip can perform multiple accesses and pre-charges during one clock cycle. The SRAM chip can be used for direct memory accesses such that the processor does not need to arbitrate access to the memory.

Abstract: RAM cells having a substantially balanced number of N-MOS and P-MOS transistors are disclosed. In a two-port RAM cell the invention uses an N read-write port comprising N-MOS transistors and a P read-port comprising P-MOS transistors. In a three-port RAM cell having one read-write port, the invention adds another N read-port comprising N-MOS transistors to the same two-port RAM cell. In effect, for each read-port added to a RAM cell, the invention alternates between a P read-port and then an N read-port. In a RAM cell having multiple N read-write-ports and multiple read-ports, the invention selects the number of P read-ports and/or the number of N read-ports such that the number of N-MOS transistors in the RAM cell are substantially the same as the number of P-MOS transistors. The invention is thus advantageous over the prior art because the invention provides a more balanced number of N-MOS and P-MOS transistors in each RAM cell, which better utilizes the layout areas.

Abstract: Within a data processing system implementing L1 and L2 caches and stream filters and buffers, prefetching of cache lines is performed in a progressive manner. In one mode, data may not be prefetched. In a second mode, two cache lines are prefetched wherein one line is prefetched into the L1 cache and the next line is prefetched into a stream buffer. In a third mode, more than two cache lines are prefetched at a time. In the third mode cache lines may be prefetched to the L1 cache and not the L2 cache, resulting in no inclusion between the L1 and L2 caches. A directory field entry provides an indication of whether or not a particular cache line in the L1 cache is also included in the L2 cache.

Abstract: Within a data processing system implementing L1 and L2 caches and stream filters and buffers, prefetching of cache lines is performed in a progressive manner. In one mode, data may not be prefetched. In a second mode, two cache lines are prefetched wherein one line is prefetched into the L1 cache and the next line is prefetched into a stream buffer. In a third mode, more than two cache lines are prefetched at a time. In the third mode cache lines may be prefetched to the L1 cache and not the L2 cache, resulting in no inclusion between the L1 and L2 caches.

Abstract: A logic analyzer is provided with probes (20) deriving the signals to be tested which are introduced into a digitizer (22) provided with comparators which carry out a digitization according to a logic system having two states. It comprises a change-over circuit (21) arranged between the probe and the digitizer, which permits associating several or all comparators with a given signal to be tested to extend its digitization to a multi-level logic system. The change-over circuit (21) is constituted by a matrix of MOS transfer gates or field effect transistors (FET's). When the multi-level logic system has at least one medium state limited by two references, the medium state is displayed on a display device (24) according to a straight line or a monotonic curve joining the two references between the beginning and the end of the medium state. When the duration of the medium state exceeds a predetermined duration, the display device (24) is switched on to display the medium state.

Abstract: A logic analyzer for plural input channels generates trigger signals for first and second triggering modes selected by a multiplexer. In the first mode, a channel selector produces a detection signal in the form of a pulse when the plural input channels simultaneously have logic states matching a reference combination input to the channel selector. In the second mode, the channel selector produces a detection signal in the form of a pulse corresponding to the logic state of a channel selected by a channel selection signal input to the channel selector. The first mode triggering signal exhibits a digital transition when the pulse endures at least as long as a target time period determined by a target count times the interval between clock pulses while the second mode trigger signal exhibits a digital transition when the pulse terminates before enduring for the target time period.