Abstract: A memory comprising memory cells wherein the memory is configured to operate in a normal voltage mode and a low voltage mode. The method includes during the normal voltage mode, operating the memory cells at a first voltage across each of the memory cells. The method further includes upon transitioning from the normal voltage mode to the low voltage mode, operating the memory cells at a second voltage across each of the memory cells, wherein the second voltage is lower than the first voltage. The method further includes performing an access on a subset of the memory cells while maintaining the second voltage across the memory cells.

Abstract: A memory comprising memory cells wherein the memory is configured to operate in a normal voltage mode and a low voltage mode. The method includes during the normal voltage mode, operating the memory cells at a first voltage across each of the memory cells. The method further includes upon transitioning from the normal voltage mode to the low voltage mode, operating the memory cells at a second voltage across each of the memory cells, wherein the second voltage is lower than the first voltage. The method further includes performing an access on a subset of the memory cells while maintaining the second voltage across the memory cells.

Abstract: A technique for operating a memory circuit that improves performance of the memory circuit and/or power consumption for at least some operating points of the memory circuit includes adjusting a number of operational pipeline stages at least partially based on an operating point of the memory. In at least one embodiment of the invention, a method for operating a memory circuit includes selecting a mode of operating the memory circuit at least partially based on a feedback signal generated by the memory circuit. The technique includes operating the memory circuit using a number of pipeline stages based on the selected mode of operation of the memory circuit. In at least one embodiment of the invention, the technique includes sensing a timing margin associated with an individual pipeline stage and generating the feedback signal based thereon.

Abstract: A technique for operating a memory circuit that improves performance of the memory circuit and/or power consumption for at least some operating points of the memory circuit includes adjusting a number of operational pipeline stages at least partially based on an operating point of the memory. In at least one embodiment of the invention, a method for operating a memory circuit includes selecting a mode of operating the memory circuit at least partially based on a feedback signal generated by the memory circuit. The technique includes operating the memory circuit using a number of pipeline stages based on the selected mode of operation of the memory circuit. In at least one embodiment of the invention, the technique includes sensing a timing margin associated with an individual pipeline stage and generating the feedback signal based thereon.

Abstract: A portion of a memory may include a first memory block, including a first memory cell coupled to a first memory data line, a second memory block, including a second memory cell coupled to a second memory data line, and a latch, having a first terminal and a second terminal. The portion of the memory may further include a first N-channel transistor, having a first current electrode coupled to the first terminal of the latch, having a second current electrode coupled to a first power supply voltage, and having a control electrode coupled to the first memory data line. The portion of the memory may further include a second N-channel transistor, having a first current electrode coupled to the first terminal of the latch, having a second current electrode coupled to the first power supply voltage, and having a control electrode coupled to the second memory data line.

Abstract: A data path of a memory is from an array of the memory, through a sense amplifier, through NOR gates, through N channel transistors, and through a latch that provides an output. The sense amplifier provides complementary data to the NOR gates which provide an output to the N channel transistors. The NOR gates provide outputs to the latch. This has the affect of providing outputs to gates of one inverter and drains of another inverter. Additional P channel transistors are in series with the inverters of the latch. The P channel transistor that is in series with the inverters whose drains are receiving the signal is made to be nonconductive by the output of the NOR gate to block current flow to the N channel transistor that is providing the input to the latch. The blocking of the current reduces the amount of current that the N channel transistor has to sink. This enables the N channel transistor, even at a reduced voltage, to be sufficiently conductive to flip the state of the latch.

Abstract: A data path of a memory is from an array of the memory, through a sense amplifier, through NOR gates, through N channel transistors, and through a latch that provides an output. The sense amplifier provides complementary data to the NOR gates which provide an output to the N channel transistors. The NOR gates provide outputs to the latch. This has the affect of providing outputs to gates of one inverter and drains of another inverter. Additional P channel transistors are in series with the inverters of the latch. The P channel transistor that is in series with the inverters whose drains are receiving the signal is made to be nonconductive by the output of the NOR gate to block current flow to the N channel transistor that is providing the input to the latch. The blocking of the current reduces the amount of current that the N channel transistor has to sink. This enables the N channel transistor, even at a reduced voltage, to be sufficiently conductive to flip the state of the latch.

Abstract: A portion of a memory may include a first memory block, comprising a first memory cell coupled to a first memory data line, a second memory block, comprising a second memory cell coupled to a second memory data line, and a latch, having a first terminal and a second terminal. The portion of the memory may further include a first N-channel transistor, having a first current electrode coupled to the first terminal of the latch, having a second current electrode coupled to a first power supply voltage, and having a control electrode coupled to the first memory data line. The portion of the memory may further include a second N-channel transistor, having a first current electrode coupled to the first terminal of the latch, having a second current electrode coupled to the first power supply voltage, and having a control electrode coupled to the second memory data line.