Patents by Inventor Huy Binh LE

Huy Binh LE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11799054
    Abstract: A light emitting structure has quantum wells grown on a coalesced substrate stemming from nanocolumns. The crystal structure is very low in defects and efficiency of light production is good. By growing the nanocolumns at a lower temperature, the quantum well structure is better matched to the coalesced substrate and efficiency is improved.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: October 24, 2023
    Inventors: Najeeb Ashraf Khalid, Huy Binh Le, Hong Nhung Tran
  • Patent number: 11705900
    Abstract: Circuitry for controlling current between a load and a power supply, the circuitry comprising: an output stage comprising: an input node configured to be coupled to the power supply; and an output node configured to be coupled to the load; and one or more control nodes for controlling a conduction path between the input node and the output node; and protection circuitry coupled to the one or more control nodes, the protection circuitry configured to break the conduction path between the input node and the output node when a load voltage at the output node exceeds a supply voltage at the input node, wherein the protection circuitry comprises: an active protection circuit configured to break the conduction path when the supply voltage exceeds an operational threshold of the active protection circuit; and a passive protection circuit configured to break the conduction path when the supply voltage is below an operation threshold of the active protection circuit.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: July 18, 2023
    Assignee: Cirrus Logic, Inc.
    Inventors: Andrew Buist, Mark McCloy-Stevens, Dave Smith, Gordon Russell, Huy Binh Le
  • Patent number: 11536767
    Abstract: The present disclosure relates to self-test circuitry for a system that includes one or more current control subsystems, each current control subsystem having a load terminal for coupling the current control subsystem to a load. The self-test circuitry comprises: a signal path associated with each current control subsystem, each signal path configured to selectively couple a measurement node to the load terminal of the current control subsystem, wherein the measurement node is common to all of the signal paths; voltage detection circuitry; and test voltage source circuitry configured to provide a test voltage to the measurement node. The voltage detection circuitry is operable to output a signal indicative of a fault condition if a voltage detected at the measurement node differs from the test voltage when the measurement node is coupled to the load terminal.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: December 27, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: James Wells, Saurabh Singh, Huy Binh Le, Gavin Wilson, Niall McGurnaghan, Simon R. Foster, Mark McCloy-Stevens
  • Patent number: 11393952
    Abstract: The array of gallium-nitride (GaN) nanocolumns have quantum wells in a polar c-plane or in a semi-polar plane to emit light directed to ends of the nanocolumns and an interstitial filler material with light emitted in the nanocolumns being guided to exit from an end of the nanocolumns.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: July 19, 2022
    Inventors: Najeeb Ashraf Khalid, Huy Binh Le, Alexander Novikov
  • Publication number: 20220069163
    Abstract: The array of gallium-nitride (GaN) nanocolumns have quantum wells in a polar c-plane or in a semi-polar plane to emit light directed to ends of the nanocolumns and an interstitial filler material with light emitted in the nanocolumns being guided to exit from an end of the nanocolumns.
    Type: Application
    Filed: November 20, 2020
    Publication date: March 3, 2022
    Inventors: Najeeb Ashraf KHALID, Huy Binh LE, Alexander NOVIKOV
  • Patent number: 11094846
    Abstract: The array of gallium-nitride (GaN) nanocolumns have quantum wells in a polar c-plane or in a semi-polar plane to emit light directed to ends of the nanocolumns and an interstitial filler material with light emitted in the nanocolumns being guided to exit from an end of the nanocolumns.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: August 17, 2021
    Inventors: Najeeb Ashraf Khalid, Huy Binh Le, Alexander Novikov
  • Publication number: 20210242865
    Abstract: Circuitry for controlling current between a load and a power supply, the circuitry comprising: an output stage comprising: an input node configured to be coupled to the power supply; and an output node configured to be coupled to the load; and one or more control nodes for controlling a conduction path between the input node and the output node; and protection circuitry coupled to the one or more control nodes, the protection circuitry configured to break the conduction path between the input node and the output node when a load voltage at the output node exceeds a supply voltage at the input node, wherein the protection circuitry comprises: an active protection circuit configured to break the conduction path when the supply voltage exceeds an operational threshold of the active protection circuit; and a passive protection circuit configured to break the conduction path when the supply voltage is below an operation threshold of the active protection circuit.
    Type: Application
    Filed: January 27, 2021
    Publication date: August 5, 2021
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Andrew BUIST, Mark MCCLOY-STEVENS, Dave SMITH, Gordon RUSSELL, Huy Binh LE
  • Publication number: 20210148968
    Abstract: The present disclosure relates to self-test circuitry for a system that includes one or more current control subsystems, each current control subsystem having a load terminal for coupling the current control subsystem to a load. The self-test circuitry comprises: a signal path associated with each current control subsystem, each signal path configured to selectively couple a measurement node to the load terminal of the current control subsystem, wherein the measurement node is common to all of the signal paths; voltage detection circuitry; and test voltage source circuitry configured to provide a test voltage to the measurement node. The voltage detection circuitry is operable to output a signal indicative of a fault condition if a voltage detected at the measurement node differs from the test voltage when the measurement node is coupled to the load terminal.
    Type: Application
    Filed: October 8, 2020
    Publication date: May 20, 2021
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: James WELLS, Saurabh SINGH, Huy Binh LE, Gavin WILSON, Niall MCGURNAGHAN, Simon R. FOSTER, Mark MCCLOY-STEVENS