Abstract: A method of fabricating a dielectric film includes depositing a first precursor on a substrate. The first precursor includes a cyclic carbosiloxane group comprising a six-membered ring. The method also includes depositing a second precursor on the substrate. The first precursor and the second precursor form a preliminary film on the substrate, and the second precursor includes silicon, carbon, and hydrogen. The method further includes exposing the preliminary film to energy from an energy source to form a porous dielectric film.

Abstract: An embodiment of an apparatus may include a substrate and a semiconductor structure disposed on the substrate, where the semiconductor structure comprises a plurality of layers of material and where at least one layer of the plurality of layers of material comprises carbon-nitride-carbon (CNC). Other embodiments are disclosed and claimed.

Abstract: A low sidelobe beam forming method and dual-beam antenna schematic are disclosed, which may preferably be used for 3-sector and 6-sector cellular communication system. Complete antenna combines 2-, 3- or -4 columns dual-beam sub-arrays (modules) with improved beam-forming network (BFN). The modules may be used as part of an array, or as an independent 2-beam antenna. By integrating different types of modules to form a complete array, the present invention provides an improved dual-beam antenna with improved azimuth sidelobe suppression in a wide frequency band of operation, with improved coverage of a desired cellular sector and with less interference being created with other cells. Advantageously, a better cell efficiency is realized with up to 95% of the radiated power being directed in a desired cellular sector.

Abstract: A low sidelobe beam forming method and dual-beam antenna schematic are disclosed, which may preferably be used for 3-sector and 6-sector cellular communication system. Complete antenna combines 2-, 3- or -4 columns dual-beam sub-arrays (modules) with improved beam-forming network (BFN). The modules may be used as part of an array, or as an independent 2-beam antenna. By integrating different types of modules to form a complete array, the present invention provides an improved dual-beam antenna with improved azimuth sidelobe suppression in a wide frequency band of operation, with improved coverage of a desired cellular sector and with less interference being created with other cells. Advantageously, a better cell efficiency is realized with up to 95% of the radiated power being directed in a desired cellular sector.

Abstract: Techniques for testing and validating content generated by applications provided by a provider network are described. A test execution service is disclosed that provides users with a framework for testing the functionality of an application provided by a provider network. A content validation service is disclosed that provides users with a framework for validating content generated by the application by orchestrating the execution of objects to be validated as part of validating content generated by the application. The content validation service generates a validation result for a user by comparing expected data values corresponding to an object to be validated with corresponding actual data values. The disclosed content validation service provides users with the ability to define objects and object definitions for objects to be validated as part of validating content generated by applications provided by the provider network.

Abstract: Methods produce integrated circuit structures that include (among other components) fins extending from a first layer, source/drain structures on the fins, source/drain contacts on the source/drain structures, an insulator on the source/drain contacts defining trenches between the source/drain contacts, gate conductors in a lower portion of the trenches adjacent the fins, a first liner material lining a middle portion and an upper portion of the trenches, a fill material in the middle portion of the trenches, and a second material in the upper portion of the trenches. The first liner material is on the gate conductors in the trenches.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.

Abstract: A low sidelobe beam forming method and dual-beam antenna schematic are disclosed, which may preferably be used for 3-sector and 6-sector cellular communication system. Complete antenna combines 2-, 3- or -4 columns dual-beam sub-arrays (modules) with improved beam-forming network (BFN). The modules may be used as part of an array, or as an independent 2-beam antenna. By integrating different types of modules to form a complete array, the present invention provides an improved dual-beam antenna with improved azimuth sidelobe suppression in a wide frequency band of operation, with improved coverage of a desired cellular sector and with less interference being created with other cells. Advantageously, a better cell efficiency is realized with up to 95% of the radiated power being directed in a desired cellular sector.

Abstract: A low sidelobe beam forming method and dual-beam antenna schematic are disclosed, which may preferably be used for 3-sector and 6-sector cellular communication system. Complete antenna combines 2-, 3- or -4 columns dual-beam sub-arrays (modules) with improved beam-forming network (BFN). The modules may be used as part of an array, or as an independent 2-beam antenna. By integrating different types of modules to form a complete array, the present invention provides an improved dual-beam antenna with improved azimuth sidelobe suppression in a wide frequency band of operation, with improved coverage of a desired cellular sector and with less interference being created with other cells. Advantageously, a better cell efficiency is realized with up to 95% of the radiated power being directed in a desired cellular sector.

Abstract: A method of fabricating a dielectric film includes depositing a first precursor on a substrate. The first precursor includes a cyclic carbosiloxane group comprising a six-membered ring. The method also includes depositing a second precursor on the substrate. The first precursor and the second precursor form a preliminary film on the substrate, and the second precursor includes silicon, carbon, and hydrogen. The method further includes exposing the preliminary film to energy from an energy source to form a porous dielectric film.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.

Abstract: Methods produce integrated circuit structures that include (among other components) fins extending from a first layer, source/drain structures on the fins, source/drain contacts on the source/drain structures, an insulator on the source/drain contacts defining trenches between the source/drain contacts, gate conductors in a lower portion of the trenches adjacent the fins, a first liner material lining a middle portion and an upper portion of the trenches, a fill material in the middle portion of the trenches, and a second material in the upper portion of the trenches. The first liner material is on the gate conductors in the trenches.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.

Abstract: Structures for a field-effect transistor and methods of forming a structure for field-effect transistor. A gate electrode is arranged in a lower portion of a trench in an interlayer dielectric layer, and a liner is formed inside an upper portion of the trench and over a top surface of the interlayer dielectric layer. A dielectric material is deposited in in the upper portion of the trench and over the liner on the top surface of the interlayer dielectric layer. The dielectric material is polished with a polishing process to remove the dielectric material from the liner on the top surface of the interlayer dielectric layer and to form a cap comprised of the dielectric material in the upper portion of the trench. The liner on the interlayer dielectric layer operates as a polish stop during the polishing process.

Abstract: A tone inversion method for integrated circuit (IC) fabrication includes providing a substrate with a layer of amorphous carbon over the substrate and a patterning layer over the amorphous carbon layer. The patterning layer is etched to define a first pattern of raised structures and a complementary recessed pattern that is filled with a layer of image reverse material. The first pattern of raised structures is then removed to define a second pattern of structures comprising the image reverse material. A selective etching step is used to transfer the second pattern into a dielectric layer disposed between the layer of amorphous carbon and the substrate.

Abstract: Methods produce integrated circuit structures that include (among other components) fins extending from a first layer, source/drain structures on the fins, source/drain contacts on the source/drain structures, an insulator on the source/drain contacts defining trenches between the source/drain contacts, gate conductors in a lower portion of the trenches adjacent the fins, a first liner material lining a middle portion and an upper portion of the trenches, a fill material in the middle portion of the trenches, and a second material in the upper portion of the trenches. The first liner material is on the gate conductors in the trenches.

Abstract: Methods produce integrated circuit structures that include (among other components) fins extending from a first layer, source/drain structures on the fins, source/drain contacts on the source/drain structures, an insulator on the source/drain contacts defining trenches between the source/drain contacts, gate conductors in a lower portion of the trenches adjacent the fins, a first liner material lining a middle portion and an upper portion of the trenches, a fill material in the middle portion of the trenches, and a second material in the upper portion of the trenches. The first liner material is on the gate conductors in the trenches.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.

Abstract: At least one method, apparatus and system disclosed herein involves forming trench silicide region contact. A plurality of fins are formed on a semiconductor substrate. An epitaxial (EPI) feature is formed at a top portion of each fin of the first portion over a first portion of the fins. A gate region is formed over a second portion of the fins. A trench is formed in a portion of the gate region. A void is formed adjacent the a portion of the gate region. A first silicon feature is formed in the trench. A second silicon feature is formed in the void. Subsequently, a replacement metal gate (RMG) process is performed in the gate region. A TS cut region is formed over the trench. The first silicon feature and the second silicon feature are removed. A metallization process is performed in the void to form a contact.

Abstract: At least one method, apparatus and system disclosed herein involves forming trench silicide region contact. A plurality of fins are formed on a semiconductor substrate. An epitaxial (EPI) feature is formed at a top portion of each fin of the first portion over a first portion of the fins. A gate region is formed over a second portion of the fins. A replacement metal gate (RMG) process is performed in the gate region. A trench is formed in a portion of the gate region. A void is formed adjacent the a portion of the gate region. A first silicon feature is formed in the trench. A second silicon feature is formed in the void. A TS cut region is formed over the trench. The first silicon feature and the second silicon feature are removed. A metallization process is performed in the void to form a contact.