Patents by Inventor Huy Lai

Huy Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12330157
    Abstract: An optoelectronic tweezer device includes a transparent substrate, a semiconductor layer, a first electrode and a dielectric layer. The semiconductor layer is located above the transparent substrate and includes a first doping region, a second doping region and a transition region, wherein the transition region is located between the first doping region and the second doping region. The first electrode is located on the first doping region and is electrically connected to the first doping region. The dielectric layer is located above the semiconductor layer and has a first through hole overlapping the first electrode.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: June 17, 2025
    Assignee: Au Optronics Corporation
    Inventors: Shih-Hua Hsu, Wei-Han Chen, Ching-Wen Chen, Ying-Hui Lai
  • Publication number: 20250174499
    Abstract: A method of testing a semiconductor package includes: attaching a charge measurement unit to a carrier substrate; forming a first metallization layer over the charge measurement unit, wherein the forming of the first metallization layer induces first charges to accumulate on the charge measurement unit; performing a first test against the charge measurement unit to determine whether breakdown occurs in the charge measurement unit; and in response to determining that no breakdown occurs in the charge measurement unit, forming a second metallization layer over the first metallization layer.
    Type: Application
    Filed: January 23, 2025
    Publication date: May 29, 2025
    Inventors: CHI-HUI LAI, YANG-CHE CHEN, CHEN-HUA LIN, VICTOR CHIANG LIANG, CHWEN-MING LIU
  • Publication number: 20250140684
    Abstract: A semiconductor includes a first substrate having a device region and a ring region surrounding the device region, a first interconnect structure over the first substrate, the first interconnect structure including a first via tower and a second via tower, a first bonding layer over the first interconnect structure and including a first metal bonding feature, a second bonding layer over the first bonding layer and including a second metal bonding feature in contact with the first metal bonding feature, and a second interconnect structure over the second bonding layer and including a third via tower extending through the second interconnect structure and disposed directly over the ring region. The first via tower is electrically coupled to the second via tower by a first metal line. The first via tower is electrically coupled to the third via tower by the first metal bonding feature and the second metal bonding feature.
    Type: Application
    Filed: February 13, 2024
    Publication date: May 1, 2025
    Inventors: Chi-Hui Lai, Yang-Che Chen, Hsiang-Tai Lu, Wei-Ray Lin, Tse-Wei Liao, Ming Jun Li
  • Patent number: 12266336
    Abstract: An earphone device is provided and includes: a wireless or wired transceiver module configured to receive a first electrical signal from an electronic device via a wireless or wired transmission network; a first compensation module connected to the wireless or wired transceiver module and arranged in a streaming audio gain compensating filter of an active noise cancellation chip, where the first compensation module is used to implement a frequency response curve to calculate a frequency response of the first electrical signal in each frequency band, and to generate a first filter parameter of a target frequency response curve via a first compensation gain conversion model, so that the first filter parameter gain compensates the first electrical signal in each of the frequencies; and a first transducer connected to the first compensation module to convert the first electrical signal gain compensating into sound and then transmit the sound.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: April 1, 2025
    Assignee: REHEAR AUDIOLOGY COMPANY LTD.
    Inventors: Ming-Han Yeh, Ying-Hui Lai
  • Patent number: 12255174
    Abstract: A package includes a package substrate, an interposer over and bonded to the package substrate, a first wafer over and bonding to the interposer, and a second wafer over and bonding to the first wafer. The first wafer has independent passive device dies therein. The second wafer has active device dies therein.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo Lung Pan, Shu-Rong Chun, Chi-Hui Lai, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu
  • Patent number: 12243788
    Abstract: A method of testing a semiconductor package includes: forming a charge measurement unit over a carrier substrate; forming a first dielectric layer over the charge measurement unit; forming a first metallization layer over the dielectric layer, wherein the forming of the first metallization layer induces first charges to accumulate on the charge measurement unit; performing a first test against the charge measurement unit to determine whether breakdown occurs in the charge measurement unit; and in response to determining that no breakdown occurs in the charge measurement unit, forming a second dielectric layer over the first metallization layer.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chi-Hui Lai, Yang-Che Chen, Chen-Hua Lin, Victor Chiang Liang, Chwen-Ming Liu
  • Patent number: 12205860
    Abstract: In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die.
    Type: Grant
    Filed: July 12, 2023
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Hsien Chiang, Yu-Chih Huang, Ting-Ting Kuo, Chih-Hsuan Tai, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai, Chiahung Liu, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20250015034
    Abstract: A semiconductor structure includes a first die; a molding surrounding the first die; a redistribution layer (RDL) disposed under the first die and the molding, and including a plurality of first conductive pads and a dielectric layer surrounding the plurality of first conductive pads; a second die disposed under the RDL, and including a plurality of first die pads over the second die; and a plurality of first conductive bumps disposed between the RDL and the second die, wherein each of the plurality of first conductive bumps is electrically coupled with corresponding one of the plurality of first die pads and corresponding one of the plurality of first conductive pads, the plurality of first die pads are respectively arranged at corners of the second die, and the plurality of first conductive bumps are electrically connected in series.
    Type: Application
    Filed: July 5, 2023
    Publication date: January 9, 2025
    Inventors: TSE-WEI LIAO, YANG-CHE CHEN, CHI-HUI LAI, WEI-YU CHOU, HSIANG-TAI LU
  • Patent number: 12159624
    Abstract: A method of forming augmented corpus related to articulation disorder includes acquiring target speech feature data from a target corpus; acquiring training speech feature data from training corpora; training a conversion model to make it capable of converting training speech feature data into a respective output that is similar to the target speech feature data; receiving an augmenting source corpus and acquiring augmenting source speech feature data therefrom; converting, by the conversion model thus trained, the augmenting source speech feature data into converted speech feature data; and synthesizing the augmented corpus based on the converted speech feature data.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: December 3, 2024
    Assignees: APREVENT MEDICAL INC., NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Ying-Hui Lai, Guan-Min Ho, Chia-Yuan Chang
  • Publication number: 20240395769
    Abstract: A package includes a package substrate, an interposer over and bonded to the package substrate, a first wafer over and bonding to the interposer, and a second wafer over and bonding to the first wafer. The first wafer has independent passive device dies therein. The second wafer has active device dies therein.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 28, 2024
    Inventors: Chen-Hua Yu, Kuo Lung Pan, Shu-Rong Chun, Chi-Hui Lai, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu
  • Publication number: 20240363591
    Abstract: An embodiment includes a first package component including a first integrated circuit die and a first encapsulant at least partially surrounding the first integrated circuit die. The device also includes a redistribution structure on the first encapsulant and coupled to the first integrated circuit die. The device also includes a first thermal module coupled to the first integrated circuit die. The device also includes a second package component bonded to the first package component, the second package component including a power module attached to the first package component, the power module including active devices. The device also includes a second thermal module coupled to the power module. The device also includes a mechanical brace extending from a top surface of the second thermal module to a bottom surface of the first thermal module, the mechanical brace physically contacting the first thermal module and the second thermal module.
    Type: Application
    Filed: July 9, 2024
    Publication date: October 31, 2024
    Inventors: Chen-Hua Yu, Chi-Hui Lai, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu
  • Publication number: 20240339427
    Abstract: A package structure including at least one semiconductor die and a redistribution structure is provided. The semiconductor die is laterally encapsulated by an encapsulant, and the redistribution structure is disposed on the semiconductor die and the encapsulant and electrically connected with the semiconductor die. The redistribution structure includes signal lines and a pair of repair lines. The signal lines include a pair of first signal lines located at a first level, and each first signal line of the pair of first signal lines has a break that split each first signal line into separate first and second fragments. The pair of repair lines is located above the pair of first signal lines and located right above the break. Opposite ending portions of each repair line are respectively connected with the first and second fragments with each repair line covering the break in each first signal line.
    Type: Application
    Filed: June 13, 2024
    Publication date: October 10, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yuan Teng, Hao-Yi Tsai, Kuo-Lung Pan, Sen-Kuei Hsu, Tin-Hao Kuo, Yi-Yang Lei, Ying-Cheng Tseng, Chi-Hui Lai
  • Publication number: 20240297163
    Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.
    Type: Application
    Filed: May 12, 2024
    Publication date: September 5, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai
  • Patent number: 12081948
    Abstract: A self-fitting hearing compensation device with real-ear measurement is provided and includes: a first transducer, which receives a first test signal from a device and converts the first test signal into a first electrical signal; a first hearing compensation module, which is connected to the first transducer and performs gain compensation on the first electrical signal; a second transducer, which is connected to the first hearing compensation module, converts the gain-compensated first electrical signal into sound, and transmits the sound into an ear canal; and a third transducer, which synchronously converts the sound transmitted in the ear canal into a second electrical signal, so as to transmit the second electrical signal to the device via a wireless transmission network. In addition, a self-fitting hearing compensation method and a computer program product are also provided.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: September 3, 2024
    Assignee: GMI Technology Inc.
    Inventors: Ming-Han Yeh, Ying-Hui Lai
  • Patent number: 12074143
    Abstract: An embodiment includes a first package component including a first integrated circuit die and a first encapsulant at least partially surrounding the first integrated circuit die. The device also includes a redistribution structure on the first encapsulant and coupled to the first integrated circuit die. The device also includes a first thermal module coupled to the first integrated circuit die. The device also includes a second package component bonded to the first package component, the second package component including a power module attached to the first package component, the power module including active devices. The device also includes a second thermal module coupled to the power module. The device also includes a mechanical brace extending from a top surface of the second thermal module to a bottom surface of the first thermal module, the mechanical brace physically contacting the first thermal module and the second thermal module.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: August 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Hua Yu, Chi-Hui Lai, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu
  • Patent number: 12051666
    Abstract: A package structure including at least one semiconductor die and a redistribution structure is provided. The semiconductor die is laterally encapsulated by an encapsulant, and the redistribution structure is disposed on the semiconductor die and the encapsulant and electrically connected with the semiconductor die. The redistribution structure includes signal lines and a pair of repair lines. The signal lines include a pair of first signal lines located at a first level, and each first signal line of the pair of first signal lines has a break that split each first signal line into separate first and second fragments. The pair of repair lines is located above the pair of first signal lines and located right above the break. Opposite ending portions of each repair line are respectively connected with the first and second fragments with each repair line covering the break in each first signal line.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: July 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yuan Teng, Hao-Yi Tsai, Kuo-Lung Pan, Sen-Kuei Hsu, Tin-Hao Kuo, Yi-Yang Lei, Ying-Cheng Tseng, Chi-Hui Lai
  • Publication number: 20240243163
    Abstract: The present disclosure provides a semiconductor structure including a vertical inductor. The semiconductor structure includes a first semiconductor substrate, a first conductive layer, a first magnetic layer, and a second magnetic layer. The first semiconductor substrate has a top surface, and the first conductive layer is vertically inserted into the first semiconductor substrate from the top surface of the first semiconductor substrate. The first magnetic layer is disposed in the first semiconductor substrate and surrounds the first conductive layer. The second magnetic layer is disposed over the first conductive layer and the first magnetic layer.
    Type: Application
    Filed: January 13, 2023
    Publication date: July 18, 2024
    Inventors: WEI-YU CHOU, YANG-CHE CHEN, CHI-HUI LAI, YI-LUN YANG, HSIANG-TAI LU
  • Patent number: 12015017
    Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: June 18, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai
  • Patent number: 12009281
    Abstract: A package structure includes a semiconductor die, a redistribution circuit structure, and a metallization element. The semiconductor die has an active side and an opposite side opposite to the active side. The redistribution circuit structure is disposed on the active side and is electrically coupled to the semiconductor die. The metallization element has a plate portion and a branch portion connecting to the plate portion, wherein the metallization element is electrically isolated to the semiconductor die, and the plate portion of the metallization element is in contact with the opposite side.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: June 11, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wei Chen, Hao-Yi Tsai, Kuo-Lung Pan, Tin-Hao Kuo, Po-Yuan Teng, Chi-Hui Lai
  • Patent number: D1030668
    Type: Grant
    Filed: June 24, 2022
    Date of Patent: June 11, 2024
    Assignee: Meritor Electric Vehicles Germany GmbH
    Inventors: Cheng Shuai Lu, Han Wang Zhao, Hai Bin Li, Hui Lai Liu