Abstract: A logic circuit employing feedback controlled loads to increase the response time and minimize power consumption. A plurality of input circuits are provided, each having means for coupling a first signal to a second signal. A first load responsive to the second signal provides a means for pulling up the first signal and a second load responsive to the first signal provides a means for pulling down the second signal. A driver responsive to the first and second signals is provided for generating an output voltage.

Abstract: A fuse programming circuit having reduced energy consumption is coupled between a first potential and a second potential for providing a programmable voltage level at an output node. The electrical circuit has a fuse element having a first terminal coupled to the output node and a second terminal coupled to the first potential. The electrical circuit also has means for providing a path for passing electrical charge between the second potential and the output node, which the path between the second potential and the output node has substantially infinite resistance when the electrical charge is being transferred.

Abstract: A pulse generator circuit is disclosed which is constructed using MOSFET transistors, and which provides substantially simultaneous complementary output pulses in response to a clock input signal. In one embodiment, the output pulses are provided in response to the positive edge of the clock input signal, and in a second embodiment, the output pulses are provided in response to a negative edge of the clock input signal. The transconductances of the transistors are set to enhance the circuit performance.

Abstract: A pulse generator circuit is disclosed which is constructed using MOSFET transistors, and which provides substantially simultaneous complementary output pulses in response to a clock input signal. In one embodiment, the output pulses are provided in response to the positive edge of the clock input signal, and in a second embodiment, the output pulses are provided in response to a negative edge of the clock input signal. The transconductances of the transistors are set to enhance the circuit performance.