Patents by Inventor Huy V. Nguyen

Huy V. Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9182985
    Abstract: Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: November 10, 2015
    Assignee: Intel Corporation
    Inventors: Yen-Kuang Chen, William W. Macy, Jr., Matthew Holliman, Eric L. Debes, Minerva M. Yeung, Huy V. Nguyen, Julien Sebot
  • Patent number: 9170814
    Abstract: Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: October 27, 2015
    Assignee: Intel Corporation
    Inventors: Yen-Kuang Chen, William W. Macy, Matthew Holliman, Eric L. Debes, Minerva M. Yeung, Huy V. Nguyen, Julien Sebot
  • Patent number: 9170815
    Abstract: Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: October 27, 2015
    Assignee: Intel Corporation
    Inventors: Yen-Kuang Chen, William W. Macy, Jr., Matthew Holliman, Eric L. Debes, Minerva M. Yeung, Huy V. Nguyen, Julien Sebot
  • Publication number: 20150154023
    Abstract: Method, apparatus, and program means for shuffling data. The method of one embodiment comprises receiving a first operand having a set of L data elements and a second operand having a set of L control elements. For each control element, data from a first operand data element designated by the individual control element is shuffled to an associated resultant data element position if its flush to zero field is not set and a zero is placed into the associated resultant data element position if its flush to zero field is not set.
    Type: Application
    Filed: December 30, 2014
    Publication date: June 4, 2015
    Applicant: INTEL CORPORATION
    Inventors: William W. Macy, JR., Eric L. Debes, Patrice L. Roussel, Huy V. Nguyen
  • Publication number: 20150121039
    Abstract: Method, apparatus, and program means for shuffling data. The method of one embodiment comprises receiving a first operand having a set of L data elements and a second operand having a set of L control elements. For each control element, data from a first operand data element designated by the individual control element is shuffled to an associated resultant data element position if its flush to zero field is not set and a zero is placed into the associated resultant data element position if its flush to zero field is not set.
    Type: Application
    Filed: December 30, 2014
    Publication date: April 30, 2015
    Applicant: Intel Corporation
    Inventors: William W. Macy, JR., Eric L. Debes, Patrice L. Roussel, Huy V. Nguyen
  • Patent number: 9003375
    Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing optional logging of debug activities in a real time instruction tracing log. For example, in one embodiment, such means may include an integrated circuit having means for initiating instruction tracing for instructions of a traced application, mode, or code region, as the instructions are executed by the integrated circuit; means for generating a plurality of packets to a debug log describing the instruction tracing; means for initiating an alternative mode of execution within the integrated circuit; and means for suppressing indication of entering the alternative mode of execution. Additional and alternative means may be implemented for selectively causing an integrated circuit to operate in accordance with an invisible trace mode or a visible trace mode upon transition to the alternative mode of execution.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: April 7, 2015
    Assignee: Intel Corporation
    Inventors: Jason W. Brandt, Peter Lachner, Huy V. Nguyen, Jonathan J. Tyler
  • Patent number: 8782377
    Abstract: Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: July 15, 2014
    Assignee: Intel Corporation
    Inventors: Julien Sebot, William W. Macy, Eric Debes, Huy V. Nguyen
  • Patent number: 8745358
    Abstract: Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: June 3, 2014
    Assignee: Intel Corporation
    Inventors: Julien Sebot, William W. Macy, Eric Debes, Huy V. Nguyen
  • Patent number: 8688959
    Abstract: Method, apparatus, and program means for shuffling data. The method of one embodiment comprises receiving a first operand having a set of L data elements and a second operand having a set of L control elements. For each control element, data from a first operand data element designated by the individual control element is shuffled to an associated resultant data element position if its flush to zero field is not set and a zero is placed into the associated resultant data element position if its flush to zero field is not set.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: April 1, 2014
    Assignee: Intel Corporation
    Inventors: William W. Macy, Jr., Eric L. Debes, Patrice L. Roussel, Huy V. Nguyen
  • Publication number: 20130297917
    Abstract: An apparatus and method are described for real time instruction tracing. For example, a method according to one embodiment comprises: recording user specified address ranges for which tracing is required; monitoring a next linear instruction pointer (NLIP) values and/or branch linear instruction pointer (BLIP) values to determine if address range has been entered; when the range is entered, compressing the NLIP and/or BLIP values and constructing fixed length packets containing the tracing data; and transferring the fixed length packets to a memory execution cluster.
    Type: Application
    Filed: March 30, 2012
    Publication date: November 7, 2013
    Inventors: Huy V. Nguyen, Jason W. Brandt, Jonathan J. Tyler
  • Publication number: 20130263093
    Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing optional logging of debug activities in a real time instruction tracing log. For example, in one embodiment, such means may include an integrated circuit having means for initiating instruction tracing for instructions of a traced application, mode, or code region, as the instructions are executed by the integrated circuit; means for generating a plurality of packets to a debug log describing the instruction tracing; means for initiating an alternative mode of execution within the integrated circuit; and means for suppressing indication of entering the alternative mode of execution. Additional and alternative means may be implemented for selectively causing an integrated circuit to operate in accordance with an invisible trace mode or a visible trace mode upon transition to the alternative mode of execution.
    Type: Application
    Filed: December 30, 2011
    Publication date: October 3, 2013
    Inventors: Jason W. Brandt, Peter Lachner, Huy V. Nguyen, Jonathan J. Tyler
  • Publication number: 20130212359
    Abstract: Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
    Type: Application
    Filed: March 15, 2013
    Publication date: August 15, 2013
    Inventors: Julien Sebot, William W. Macy, JR., Eric L. Debes, Huy V. Nguyen
  • Patent number: 8510363
    Abstract: Method, apparatus, and program means for nonlinear filtering and deblocking applications utilizing SIMD sign and absolute value operations. The method of one embodiment comprises receiving first data for a first block and second data for a second block. The first data and said second data are comprised of a plurality of rows and columns of pixel data. A block boundary between the first block and the second block is characterized. A correction factor for a deblocking algorithm is calculated with a first instruction for a sign operation that multiplies and with a second instruction for an absolute value operation. Data for pixels located along said block boundary between the first and second block are corrected.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: August 13, 2013
    Assignee: Intel Corporation
    Inventors: William W. Macy, Jr., Huy V. Nguyen
  • Publication number: 20130007417
    Abstract: Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
    Type: Application
    Filed: September 4, 2012
    Publication date: January 3, 2013
    Inventors: Julien Sebot, William W. Macy, Eric Debes, Huy V. Nguyen
  • Publication number: 20130007416
    Abstract: Method, apparatus, and program means for shuffling data. The method of one embodiment comprises receiving a first operand having a set of L data elements and a second operand having a set of L control elements. For each control element, data from a first operand data element designated by the individual control element is shuffled to an associated resultant data element position if its flush to zero field is not set and a zero is placed into the associated resultant data element position if its flush to zero field is not set.
    Type: Application
    Filed: September 10, 2012
    Publication date: January 3, 2013
    Inventors: William W. Macy, JR., Eric L. Debes, Patrice L. Roussel, Huy V. Nguyen
  • Publication number: 20120331272
    Abstract: Method, apparatus, and program means for nonlinear filtering and deblocking applications utilizing SIMD sign and absolute value operations. The method of one embodiment comprises receiving first data for a first block and second data for a second block. The first data and said second data are comprised of a plurality of rows and columns of pixel data. A block boundary between the first block and the second block is characterized. A correction factor for a deblocking algorithm is calculated with a first instruction for a sign operation that multiplies and with a second instruction for an absolute value operation. Data for pixels located along said block boundary between the first and second block are corrected.
    Type: Application
    Filed: September 4, 2012
    Publication date: December 27, 2012
    Inventors: William W. Macy, JR., Huy V. Nguyen
  • Publication number: 20120272047
    Abstract: Method, apparatus, and program means for shuffling data. The method of one embodiment comprises receiving a first operand having a set of L data elements and a second operand having a set of L control elements. For each control element, data from a first operand data element designated by the individual control element is shuffled to an associated resultant data element position if its flush to zero field is not set and a zero is placed into the associated resultant data element position if its flush to zero field is not set.
    Type: Application
    Filed: July 2, 2012
    Publication date: October 25, 2012
    Inventors: William W. Macy, JR., Eric L. Debes, Patrice L. Roussel, Huy V. Nguyen
  • Publication number: 20120233443
    Abstract: Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
    Type: Application
    Filed: May 22, 2012
    Publication date: September 13, 2012
    Inventors: Julien Sebot, William W. Macy, Eric Debes, Huy V. Nguyen
  • Patent number: 8225075
    Abstract: Method, apparatus, and program means for shuffling data. The method of one embodiment comprises receiving a first operand having a set of L data elements and a second operand having a set of L control elements. For each control element, data from a first operand data element designated by the individual control element is shuffled to an associated resultant data element position if its flush to zero field is not set and a zero is placed into the associated resultant data element position if its flush to zero field is not set.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: July 17, 2012
    Assignee: Intel Corporation
    Inventors: William W. Macy, Jr., Eric L. Debes, Patrice L. Roussel, Huy V. Nguyen
  • Patent number: 8214626
    Abstract: Method, apparatus, and program means for shuffling data. The method of one embodiment comprises receiving a first operand having a set of L data elements and a second operand having a set of L control elements. For each control element, data from a first operand data element designated by the individual control element is shuffled to an associated resultant data element position if its flush to zero field is not set and a zero is placed into the associated resultant data element position if its flush to zero field is not set.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: July 3, 2012
    Assignee: Intel Corporation
    Inventors: William W. Macy, Jr., Eric L. Debes, Patrice L. Roussel, Huy V. Nguyen