Abstract: The invention relates to a genetic probe, wherein the genetic probe comprises: an oligonucleotide, or an oligonucleotide analogue, with a Raman-active moiety incorporated therein, wherein the Raman-active moiety is incorporated into a base of the oligonucleotide or oligonucleotide thereof; and associated methods, uses, kits and compositions for determining a single point variant nucleotide in a target nucleic acid.

Abstract: A ferrocenyl compound having the general formula (I): (I) Het is a substituted or unsubstituted heterocyclic moiety. L1, L2 and L3 are each a linker independently selected from alkylene, alkyleneoxy, alkyleneoxyalkylene, alkylenecarbonyl, alkyleneoxycarbonyl, alkyleneamido, alkyleneoxyamido, alkenylene, alkenyleneoxy, alkenylenecarbonyl, alkenyleneamido, alkynylene, alkynyleneoxy, alkynylenecarbonyl and alkynyleneamido, all of which may be straight chain or branched, substituted or unsubstituted. R1 and R2 are each independently selected from H, substituted or unsubstituted alkyl carbonyl, substituted or unsubstituted aryl carbonyl, substituted or unsubstituted phosphate, substituted or unsubstituted phosphonate and substituted or unsubstituted phosphoramidate. M and n are each 0 or 1 and m+n?0.1.

Abstract: A ferrocenyl compound having the general formula (I): (I) Het is a substituted or unsubstituted heterocyclic moiety. L1, L2 and L3 are each a linker independently selected from alkylene, alkyleneoxy, alkyleneoxyalkylene, alkylenecarbonyl, alkyleneoxycarbonyl, alkyleneamido, alkyleneoxyamido, alkenylene, alkenyleneoxy, alkenylenecarbonyl, alkenyleneamido, alkynylene, alkynyleneoxy, alkynylenecarbonyl and alkynyleneamido, all of which may be straight chain or branched, substituted or unsubstituted. R1 and R2 are each independently selected from H, substituted or unsubstituted alkyl carbonyl, substituted or unsubstituted aryl carbonyl, substituted or unsubstituted phosphate, substituted or unsubstituted phosphonate and substituted or unsubstituted phosphoramidate. M and n are each 0 or 1 and m+n?0.

Abstract: The hydraulic braking device (10) to be installed in a turbine (2) provided with a turbine shaft (4) comprising at least one body (12) connected to the said turbine shaft (4). When the said hydraulic braking device (10) is immersed in a fluid medium, axial rotation of the turbine shaft (4) about its axis causes a movement of the said at least one body (12) with respect to the said fluid medium, this movement generating a resisting torque (T) related to the rotation speed of the turbine shaft (4) through a non-linear relation.

Abstract: This invention relates to methods of treating, managing and preventing body composition disorders, and to compounds and pharmaceutical compositions useful in such methods.

Abstract: This invention relates to methods of treating, managing and preventing pain, inflammation, cancer, and ocular diseases and disorders, and to compounds and pharmaceutical compositions useful in such methods.

Abstract: The hydraulic braking device (10) to be installed in a turbine (2) provided with a turbine shaft (4) comprising at least one body (12) connected to the said turbine shaft (4). When the said hydraulic braking device (10) is immersed in a fluid medium, axial rotation of the turbine shaft (4) about its axis causes a movement of the said at least one body (12) with respect to the said fluid medium, this movement generating a resisting torque (T) related to the rotation speed of the turbine shaft (4) through a non-linear relation.

Abstract: A saturation select apparatus and method are implemented. Late stage logic blocks in an adder are provided which combine saturation select control signals with sum generating signals. A first saturation select control is asserted in response to an unsigned saturated instruction, and a second saturation select control is asserted in response to a signed saturated instruction. If either select control is asserted, each logic block outputs a corresponding bit of a respective saturation value. In response to a modulo mode instruction, both select control signals are negated, and each logic block outputs a corresponding bit of the arithmetic operation (sum or difference) implemented by the instruction.

Abstract: An apparatus for saturation detection and a method therefor are implemented. Selection circuitry selects a data value signal for outputting between an output from an adder receiving a pair of input operands, and a plurality of saturation value signals. Each input operand may include a plurality of subvector operands of a preselected data type, each data type has having a corresponding length. The selection circuitry selects the data value signal in response to a plurality of second signals. The second signals are generated from carry-out signals from the subvector operands, and first signals that are generated using instruction information for the executing instruction. The second signals may be generated by logically combining the first signals with carry propagate, carry generate and carry-out signals from carry lookahead logic receiving the subvector operands as input.

Abstract: An apparatus for compare and maximum/minimum and a method therefor are implemented. Selection circuitry selects a data value signal for outputting between an a pair of vector operands and “true” and “false” comparison value signals for the corresponding operand data type. Each input operand may include a plurality of subvector operands of a preselected data type, each data type has having a corresponding length. The selection circuitry selects the data value signal in response to a plurality of second signals. The second signals are generated from carry-out signals from the subvector operands, and first signals that are generated using instruction information for the executing instruction. The second signals may be generated by logically combining the first signals with carry propagate, carry generate and carry-out signals from carry lookahead logic receiving the subvector operands as input.

Abstract: Floating-point compare apparatus and methods are implemented. An adder generates a difference in moduli of first and second input operands. A sign bit of the second input operand provides a carry-in bit to an adder. In a first embodiment, the first and second input operands correspond to first and second source operands of the executing floating-point compare instruction. Comparison logic generates the compare result in response to a sign bit of the difference, sign bits of the first and second input operands, and a signal that is asserted if the operands are equal, and if the floating-point compare instruction being executed is A≧B, and negated otherwise. In a second embodiment, the first and second input operands are derived from the first and second source operands via switching logic that interchanges the operands in response to predecoded instruction information.

Abstract: An apparatus and method for performing partial logical shifts of a multiple-word logical signal is implemented. Portions of an input logical signal to be shifted are input to a plurality of barrel shifters. Each barrel shifter performs a rotation of its associated input portion. Each corresponding rotated portion output therefrom is masked with a preselected mask having m trailing zero bits, for a left shift, or m leading zero bits, for a right shift. Rotated portions from barrel shifters succeeding, for a left shift, or preceding, for a right shift, the barrel shifter associated with the corresponding rotated portion are masked with a complementary mask and logically combined with the masked rotated portion from the corresponding barrel shifter to form a corresponding portion of the shifted output signal.