Abstract: Provided are computer-implemented methods and systems for implementing and utilizing an audio and visual asset matching platform. The audio and visual asset matching platform may include a first interface, a digital asset creation platform, an asset matching engine, and a user feedback engine. The first interface may be configured to select at least one master digital asset. The digital asset creation platform may be configured to create digital assets, the digital assets comprising at least one of text, audio, image, video, 3D/4D virtual environments, and animation files and metadata. The asset matching engine may be configured to match digital assets and generate at least one output digital asset. The user feedback engine may be configured to monitor and analyze behavior in response to receipt of at least one output digital asset and generate feedback metrics to improve the matching of the asset matching engine.

Abstract: Provided are computer-implemented methods and systems for implementing and utilizing an audio and visual asset matching platform. The audio and visual asset matching platform may include a first interface, a digital asset creation platform, an asset matching engine, and a user feedback engine. The first interface may be configured to select at least one master digital asset. The digital asset creation platform may be configured to create digital assets, the digital assets comprising at least one of text, audio, image, video, 3D/4D virtual environments, and animation files and metadata. The asset matching engine may be configured to match digital assets and generate at least one output digital asset. The user feedback engine may be configured to monitor and analyze behavior in response to receipt of at least one output digital asset and generate feedback metrics to improve the matching of the asset matching engine.

Abstract: Apparatuses, master-slave detect circuits, memories, and methods are disclosed. One such method includes performing a master detect phase during which a memory unit in a memory group is determined to be a master memory unit, determining at each memory unit its location relative to other memory units, and determining at each memory unit its location in the memory group based on a total number of slave memory units and its location relative to other memory units.

Abstract: An example disclosed media processing device includes a housing defining a media receiving area configured to receive the media; a first media support arm extending from the housing proximate the media receiving area for engaging a first end of the media, wherein the first media support arm is biased to slidably translate along the housing to provide a holding force to the first side of the media, wherein the first media support arm includes a first locking element; a media cover configured to move between a closed position and an open position, the media cover including a second locking element, wherein the first locking element of the first media support arm is configured to engage the second locking element of the media cover when the media cover is in the closed position.

Abstract: Memories containing command decoder, chip enable, and signal truncation circuits are disclosed. One such command decoder circuit may include command decoder logic configured to receive command signals and output a decoded command to an interconnect bus responsive to a chip select signal having an active state. Decoder circuits may also prevent coupling commands to the interconnect bus based on the receipt of chip select signals having inactive states. Chip enable circuits having control logic are configured to receive chip select signals and provide the chip select signals to an interconnect bus responsive to receiving a valid command. Chip enable circuits may also prevent coupling chip select signals to the interconnect bus from chip enable signals based on the receipt of invalid command signals. Signal truncation circuits may be used to shorten and/or shift chip select signals to increase timing margins and improve the reliability of command execution by memories.

Abstract: Embodiments of a data capture system and method may be used in a variety of devices, such as in memory controllers and memory devices. The data capture system and method may generate a first set of periodic signals and a second set of periodic signals that differs from the first set. Either the first set of periodic signals or the second set of periodic signals may be selected and used to generate a set of data capture signals. The selection of either the first set or the second set may be made on the basis of the number of serial data digits in a previously captured burst of data. The data capture signals may then be used to capture a burst of serial data digits.

Abstract: Systems, methods, and other embodiments associated with providing obstacle-avoidance bus routing for an integrated circuit design are described. In one embodiment, a bus routing tool is disclosed that generates a plurality of escape nodes to construct a three-dimensional routing solution graph. The bus routing tool probes a design space of the integrated circuit design to dynamically determine a location of each escape node while avoiding path blockages within the design space. By traversing the three-dimensional routing solution graph from a leaf escape node near a target location within the design space back to a root escape node near a source location within the design space, a candidate routing solution for routing a signal bus from the source location to the target location can be determined.

Abstract: Systems, methods, and other embodiments associated with providing obstacle-avoidance bus routing for an integrated circuit design are described. In one embodiment, a bus routing tool is disclosed that generates a plurality of escape nodes to construct a three-dimensional routing solution graph. The bus routing tool probes a design space of the integrated circuit design to dynamically determine a location of each escape node while avoiding path blockages within the design space. By traversing the three-dimensional routing solution graph from a leaf escape node near a target location within the design space back to a root escape node near a source location within the design space, a candidate routing solution for routing a signal bus from the source location to the target location may be determined.

Abstract: Memories containing command decoder, chip enable, and signal truncation circuits are disclosed. One such command decoder circuit may include command decoder logic configured to receive command signals and output a decoded command to an interconnect bus responsive to a chip select signal having an active state. Decoder circuits may also prevent coupling commands to the interconnect bus based on the receipt of chip select signals having inactive states. Chip enable circuits having control logic are configured to receive chip select signals and provide the chip select signals to an interconnect bus responsive to receiving a valid command. Chip enable circuits may also prevent coupling chip select signals to the interconnect bus from chip enable signals based on the receipt of invalid command signals. Signal truncation circuits may be used to shorten and/or shift chip select signals to increase timing margins and improve the reliability of command execution by memories.

Abstract: Devices, systems and methods for a portable printer are provided. Personnel utilize features of the printer to manage products, store information on labels, and aid in shipping. A low battery shut-off feature shuts down the printer at a set battery power percentage; a battery charge control feature controls battery charging to stay within a set range of state of charge values to ensure longer battery life; a ribbon cartridge insertion feature allows for easy replacement of the ribbon cartridge; ribbon cartridge locating features lock the ribbon cartridge into place for printing; a ribbon guiding feature adjusts the ribbon during printing to reduce wrinkles; an RFID coupler mounting feature mounts and shields an RFID coupler inside the printer; a media guide locking feature fixes the media position to prevent misalignment; and a media alignment feature allows the user to properly align the media with the printhead during installation.

Abstract: Apparatuses, master-slave detect circuits, memories, and methods are disclosed. One such method includes performing a master detect phase during which a memory unit in a memory group is determined to be a master memory unit, determining at each memory unit its location relative to other memory units, and determining at each memory unit its location in the memory group based on a total number of slave memory units and its location relative to other memory units.

Abstract: Memories containing command decoder, chip enable, and signal truncation circuits are disclosed. One such command decoder circuit may include command decoder logic configured to receive command signals and output a decoded command to an interconnect bus responsive to a chip select signal having an active state. Decoder circuits may also prevent coupling commands to the interconnect bus based on the receipt of chip select signals having inactive states. The memory further may include chip enable circuits having control logic configured to receive chip select signals and provide the chip select signals to an interconnect bus responsive to receiving a valid command. Chip enable circuits may also prevent coupling chip select signals to the interconnect bus from chip enable signals based on the receipt of invalid command signals. Signal truncation circuits may be used to shorten and/or shift chip select signals to increase timing margins and improve the reliability of command execution by memories.

Abstract: Apparatuses, master-slave detect circuits, memories, and methods are disclosed. One such method includes performing a master detect phase during which a memory unit in a memory group is determined to be a master memory unit, determining at each memory unit its location relative to other memory units, and determining at each memory unit its location in the memory group based on a total number of slave memory units and its location relative to other memory units.

Abstract: Embodiments of a data capture system and method may be used in a variety of devices, such as in memory controllers and memory devices. The data capture system and method may generate a first set of periodic signals and a second set of periodic signals that differs from the first set. Either the first set of periodic signals or the second set of periodic signals may be selected and used to generate a set of data capture signals. The selection of either the first set or the second set may be made on the basis of the number of serial data digits in a previously captured burst of data. The data capture signals may then be used to capture a burst of serial data digits.

Abstract: Embodiments of a data capture system and method may be used in a variety of devices, such as in memory controllers and memory devices. The data capture system and method may generate a first set of periodic signals and a second set of periodic signals that differs from the first set. Either the first set of periodic signals or the second set of periodic signals may be selected and used to generate a set of data capture signals. The selection of either the first set or the second set may be made on the basis of the number of serial data digits in a previously captured burst of data. The data capture signals may then be used to capture a burst of serial data digits.

Abstract: Apparatuses, master-slave detect circuits, memories, and methods are disclosed. One such method includes performing a master detect phase during which a memory unit in a memory group is determined to be a master memory unit, determining at each memory unit its location relative to other memory units, and determining at each memory unit its location in the memory group based on a total number of slave memory units and its location relative to other memory units.

Abstract: Apparatuses, master-slave detect circuits, memories, and methods are disclosed. One such method includes performing a master detect phase during which a memory unit in a memory group is determined to be a master memory unit, determining at each memory unit its location relative to other memory units, and determining at each memory unit its location in the memory group based on a total number of slave memory units and its location relative to other memory units.

Abstract: Apparatuses, master-slave detect circuits, memories, and methods are disclosed. One such method includes performing a master detect phase during which a memory unit in a memory group is determined to be a master memory unit, determining at each memory unit its location relative to other memory units, and determining at each memory unit its location in the memory group based on a total number of slave memory units and its location relative to other memory units.

Abstract: Devices, systems and methods for a portable printer are provided. Personnel utilize features of the printer to manage products, store information on labels, and aid in shipping. A low battery shut-off feature shuts down the printer at a set battery power percentage; a battery charge control feature controls battery charging to stay within a set range of state of charge values to ensure longer battery life; a ribbon cartridge insertion feature allows for easy replacement of the ribbon cartridge; ribbon cartridge locating features lock the ribbon cartridge into place for printing; a ribbon guiding feature adjusts the ribbon during printing to reduce wrinkles; an RFID coupler mounting feature mounts and shields an RFID coupler inside the printer; a media guide locking feature fixes the media position to prevent misalignment; and a media alignment feature allows the user to properly align the media with the printhead during installation.

Abstract: Memories containing command decoder, chip enable, and signal truncation circuits are disclosed. One such command decoder circuit may include command decoder logic configured to receive command signals and output a decoded command to an interconnect bus responsive to a chip select signal having an active state. Decoder circuits may also prevent coupling commands to the interconnect bus based on the receipt of chip select signals having inactive states. The memory further may include chip enable circuits having control logic configured to receive chip select signals and provide the chip select signals to an interconnect bus responsive to receiving a valid command. Chip enable circuits may also prevent coupling chip select signals to the interconnect bus from chip enable signals based on the receipt of invalid command signals. Signal truncation circuits may be used to shorten and/or shift chip select signals to increase timing margins and improve the reliability of command execution by memories.