Abstract: The invention relates to novel ebsulfur analogues and novel pharmaceutical compositions comprising ebsulfur analogues. The invention also relates to novel methods of treating infections caused by fungal species comprising administration of ebselen, ebsulfur, and ebsulfur analogues.

Abstract: The invention relates to novel ebsulfur analogues and novel pharmaceutical compositions comprising ebsulfur analogues. The invention also relates to novel methods of treating infections caused by fungal species comprising administration of ebselen, ebsulfur, and ebsulfur analogues.

Abstract: Systems and methods are disclosed to control a buck converter with a first switching circuit including a first upper power transistor coupled to a first lower power transistor at a first junction; a second upper power transistor coupled to a second lower power transistor at a second junction; an inductor coupled to the first and second junctions; and a load coupled to the second junction.

Abstract: Systems and methods are disclosed to control a buck converter by performing adaptive digital pulse width modulation (ADPWM) with a plurality of upper power transistors each uniquely controlled to enable greater than 100% duty cycle for the buck converter and a lower power transistor coupled to the plurality of upper power transistors; and driving an inductor having one end coupled to the lower power transistor and the upper power transistors.

Abstract: Systems and methods are disclosed to control a buck converter with a first switching circuit including a first upper power transistor coupled to a first lower power transistor at a first junction; a second upper power transistor coupled to a second lower power transistor at a second junction; an inductor coupled to the first and second junctions; and a load coupled to the second junction.

Abstract: Systems and methods are disclosed to control a buck converter by performing adaptive digital pulse width modulation (ADPWM) with a plurality of upper power transistors each uniquely controlled to enable greater than 100% duty cycle for the buck converter and a lower power transistor coupled to the plurality of upper power transistors; and driving an inductor having one end coupled to the lower power transistor and the upper power transistors.

Abstract: Systems and methods are disclosed to control a buck converter by performing adaptive digital pulse width modulation (ADPWM) with a plurality of upper power transistors each uniquely controlled to enable greater than 100% duty cycle for the buck converter and a lower power transistor coupled to the plurality of upper power transistors; and driving an inductor having one end coupled to the lower power transistor and the upper power transistors.

Abstract: Systems and methods are disclosed to control a buck converter with a first switching circuit including a first upper power transistor coupled to a first lower power transistor at a first junction; a second switching circuit including a second upper power transistor coupled to a second lower power transistor at a second junction; an inductor coupled to the first and second junctions; and a load coupled to the second junction.

Abstract: A two-level cache memory system for use in a computer system including two primary cache memories, one for storing instruction and one for storing data. The system also includes a secondary cache memory for storing both instructions and data. The primary and secondary caches each employ their own separate tag directory. The primary caches use a virtual addressing scheme employing both virtual tags and virtual addresses. The secondary cache employs a hybrid addressing scheme which uses virtual tags and partial physical addresses. The primary and secondary caches operate in parallel unless the larger and slower secondary cache is busy performing a previous operation. Only if a "miss" is encountered in both the primary and secondary caches does the system processor access the main memory.

Abstract: A two-level cache memory system for use in a computer system including two primary cache memories, one for storing instructions and one for storing data. The system also includes a secondary cache memory for storing both instructions and data. The primary and secondary caches each employ their own separate tag directory. The primary caches use a virtual addressing scheme employing both virtual tags and virtual addresses. The secondary cache employs a hybrid addressing scheme which uses virtual tags and partial physical addresses. The primary and secondary caches operate in parallel unless the larger and slower secondary cache is busy performing a previous operation. Only if a "miss" is encountered in both the primary and secondary caches does the system processor access the main memory.