Abstract: Some embodiments include an integrated assembly having a CMOS region with fins extending along a first direction, and with gating structures extending across the fins. A circuit arrangement is associated with the CMOS region and includes a pair of the gating structures spaced by an intervening region having a missing gating structure. The circuit arrangement has a first dimension along the first direction. A second region is proximate to the CMOS region. Conductive structures are associated with the second region. Some of the conductive structures are electrically coupled with the circuit arrangement. A second dimension is a distance across said some of the conductive structures along the first direction. The conductive structures and the circuit arrangement are aligned such that the second dimension is substantially the same as the first dimension. Some embodiments include methods of forming integrated assemblies.

Abstract: Some embodiments include an integrated assembly having a CMOS region with fins extending along a first direction, and with gating structures extending across the fins. A circuit arrangement is associated with the CMOS region and includes a pair of the gating structures spaced by an intervening region having a missing gating structure. The circuit arrangement has a first dimension along the first direction. A second region is proximate to the CMOS region. Conductive structures are associated with the second region. Some of the conductive structures are electrically coupled with the circuit arrangement. A second dimension is a distance across said some of the conductive structures along the first direction. The conductive structures and the circuit arrangement are aligned such that the second dimension is substantially the same as the first dimension. Some embodiments include methods of forming integrated assemblies.

Abstract: A semiconductor device includes a substrate having an active pattern thereon, a gate electrode intersecting the active pattern, and a spacer on a sidewall of the gate electrode. The gate electrode includes a first metal pattern adjacent to the active pattern. The first metal pattern has a first portion parallel to the sidewall and a second portion parallel to the substrate. A top surface of the first portion has a descent in a direction from the spacer towards the second portion.

Abstract: A semiconductor device includes a substrate having an active pattern thereon, a gate electrode intersecting the active pattern, and a spacer on a sidewall of the gate electrode. The gate electrode includes a first metal pattern adjacent to the active pattern. The first metal pattern has a first portion parallel to the sidewall and a second portion parallel to the substrate. A top surface of the first portion has a descent in a direction from the spacer towards the second portion.

Abstract: A semiconductor device includes a substrate having an active pattern thereon, a gate electrode intersecting the active pattern, and a spacer on a sidewall of the gate electrode. The gate electrode includes a first metal pattern adjacent to the active pattern. The first metal pattern has a first portion parallel to the sidewall and a second portion parallel to the substrate. A top surface of the first portion has a descent in a direction from the spacer towards the second portion.

Abstract: A semiconductor device includes a substrate having an active pattern thereon, a gate electrode intersecting the active pattern, and a spacer on a sidewall of the gate electrode. The gate electrode includes a first metal pattern adjacent to the active pattern. The first metal pattern has a first portion parallel to the sidewall and a second portion parallel to the substrate. A top surface of the first portion has a descent in a direction from the spacer towards the second portion.

Abstract: A semiconductor device includes a gate structure crossing an active pattern of a substrate. The semiconductor device may include a gate dielectric pattern between the substrate and the gate electrode. The gate structure includes a gate electrode, a capping pattern on the gate electrode, and one or more low-k dielectric layers at least partially covering one or more sidewalls of the capping pattern. The gate structure may include spacers at opposite sidewalk of the gate electrode and separate low-k dielectric layers between the capping pattern and the spacers. The capping pattern may have a width that is smaller than a width of the gate electrode. The capping pattern has a first dielectric constant, and the one or more low-k dielectric layers have a second dielectric constant. The second dielectric constant is smaller than the first dielectric constant. The second dielectric constant may he greater than or equal to 1.

Abstract: Provided is a method of fabricating a semiconductor device, including forming an interlayered insulating layer having an opening, on a substrate; sequentially forming a first conductive pattern, a barrier pattern, and a second conductive pattern on bottom and side surfaces of the opening; and nitrifying an upper portion of the second conductive pattern to form a metal nitride layer that is spaced apart from the first conductive pattern.

Abstract: Methods of manufacturing a MOS transistor are provided. The methods may include forming first and second trenches. The methods may further include forming first metal patterns within portions of the first and second trenches. The methods may additionally include removing the first metal patterns from the second trench while at least portions of the first metal patterns remain within the first trench. The methods may also include forming a second metal layer within the first and second trenches, the second metal layer formed on the first metal patterns within the first trench.

Abstract: Methods of manufacturing a MOS transistor are provided. The methods may include forming first and second trenches. The methods may further include forming first metal patterns within portions of the first and second trenches. The methods may additionally include removing the first metal patterns from the second trench while at least portions of the first metal patterns remain within the first trench. The methods may also include forming a second metal layer within the first and second trenches, the second metal layer formed on the first metal patterns within the first trench.