Abstract: A processor having multiple functional units. The processor is capable of executing multiple instructions concurrently. An instruction issuing unit is connected to a mechanism for handling an interrupt of the processor. The interrupt handler has an instruction window (IW), which includes a vector element number (VEN) field that indicates the uncompleted elements to be executed. Upon termination of the interrupt, normal processing of the instruction issuing unit continues.

Abstract: An instruction issuing mechanism for boosting throughput of processors with multiple functional units. A Dispatch Stack (DS) and a Precedence Count Memory (PCM) are employed which allow multiple instructions to be issued per machine cycle. Additionally, instructions do no have to be issued according to their order in the instruction stream, so that non-sequential instruction issuance occurs. In this system, multiple instruction issuance and non-sequential instruction issuance policies enhance the throughput of processors with multiple functional units.

Abstract: A time division multiplex loop communication system for voice and data is disclosed with multiaccess time slot seizure and data transmission capability from all station nodes without changing the idle, nonreserved, status of the seized time slot. A method and station node apparatus sends bursty data packets from a node when a time slot is not busy serving a longer duration voice telephone call. The apparatus eliminates the need for inefficient time slot request, acknowledgement and reservation procedures which require several TDM frames to complete and which are typically longer in duration than the bursty data packet to be transmitted. All stations have access to all time slots for bursty data transmission under control of loop interface circuitry which statistically ensures the successful data transmission from all sending nodes.