Patents by Inventor Hwa Chul LEE

Hwa Chul LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9515022
    Abstract: A method for fabricating a semiconductor device includes preparing a substrate which includes a memory cell region and a peripheral circuit region; forming a buried word line in the substrate in the memory cell region; forming a planar gate structure over the substrate in the peripheral circuit region; forming a bit line structure over the substrate in the memory cell region; forming a first air spacers over a sidewalls of the planar gate structure; and forming a second air spacers over a sidewalls of the bit line structure.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: December 6, 2016
    Assignee: SK Hynix Inc.
    Inventors: Se-Han Kwon, Ill-Hee Joe, Dae-Sik Park, Hwa-Chul Lee
  • Publication number: 20160276273
    Abstract: A method for fabricating a semiconductor device includes preparing a substrate which includes a memory cell region and a peripheral circuit region; forming a buried word line in the substrate in the memory cell region; forming a planar gate structure over the substrate in the peripheral circuit region; forming a bit line structure over the substrate in the memory cell region; forming a first air spacers over a sidewalls of the planar gate structure; and forming a second air spacers over a sidewalls of the bit line structure.
    Type: Application
    Filed: June 1, 2016
    Publication date: September 22, 2016
    Inventors: Se-Han KWON, Ill-Hee JOE, Dae-Sik PARK, Hwa-Chul LEE
  • Patent number: 9379004
    Abstract: A method for fabricating a semiconductor device includes preparing a substrate which includes a memory cell region and a peripheral circuit region; forming a buried word line in the substrate in the memory cell region; forming a planar gate structure over the substrate in the peripheral circuit region; forming a bit line structure over the substrate in the memory cell region; forming a first air spacers over a sidewalls of the planar gate structure; and forming a second air spacers over a sidewalls of the bit line structure.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: June 28, 2016
    Assignee: SK Hynix Inc.
    Inventors: Se-Han Kwon, Ill-Hee Joe, Dae-Sik Park, Hwa-Chul Lee
  • Publication number: 20160181143
    Abstract: A method for fabricating a semiconductor device includes preparing a substrate which includes a memory cell region and a peripheral circuit region; forming a buried word line in the substrate in the memory cell region; forming a planar gate structure over the substrate in the peripheral circuit region; forming a bit line structure over the substrate in the memory cell region; forming a first air spacers over a sidewalls of the planar gate structure; and forming a second air spacers over a sidewalls of the bit line structure.
    Type: Application
    Filed: June 12, 2015
    Publication date: June 23, 2016
    Inventors: Se-Han KWON, Ill-Hee JOE, Dae-Sik PARK, Hwa-Chul LEE
  • Publication number: 20110248378
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a first line, a second line spaced apart from the first line, a contact formed over the first line and the second line, a fuse coupled to the contact, and a dummy pattern configured to couple the fuse to the contact.
    Type: Application
    Filed: December 17, 2010
    Publication date: October 13, 2011
    Applicant: Hynix Semiconductor Inc.
    Inventors: Hwa Chul LEE, Jeong Won Kang