Patents by Inventor Hwa-Joon Oh
Hwa-Joon Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8229989Abstract: A method for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.Type: GrantFiled: September 26, 2008Date of Patent: July 24, 2012Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Harm Peter Hofstee, Christian Jacobi, Silvia Melitta Mueller, Hwa-Joon Oh
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Patent number: 8166085Abstract: The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is configured to compute a value in a plurality of shift stages, and wherein a bit group of the shift amount is employable to affect at least one of the plurality of shift stages, thereby decreasing processing time.Type: GrantFiled: April 18, 2008Date of Patent: April 24, 2012Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Christian Jacobi, Silvia Melitta Mueller, Hiroo Nishikawa, Hwa-Joon Oh
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Patent number: 8131795Abstract: A method is provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and series of multiplexers (muxes). The carry network performs the end-around-carry function simultaneously to and independent of other required functions optimizing the functioning of the adder. Also, the use of a minimum number of muxes is also utilized to reduce mux delays.Type: GrantFiled: November 25, 2008Date of Patent: March 6, 2012Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Silvia Melitta Mueller, Hwa-Joon Oh
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Publication number: 20090077155Abstract: A method is provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and series of multiplexers (muxes). The carry network performs the end-around-carry function simultaneously to and independent of other required functions optimizing the functioning of the adder. Also, the use of a minimum number of muxes is also utilized to reduce mux delays.Type: ApplicationFiled: November 25, 2008Publication date: March 19, 2009Inventors: Sang Hoo Dhong, Silvia Melitta Mueller, Hwa-Joon Oh
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Patent number: 7490119Abstract: An apparatus and computer program product are provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and series of multiplexers (muxes). The carry network performs the end-around-carry function simultaneously to and independent of other required functions optimizing the functioning of the adder. Also, the use of a minimum number of muxes is also utilized to reduce mux delays.Type: GrantFiled: December 11, 2003Date of Patent: February 10, 2009Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Silvia Melitta Mueller, Hwa-Joon Oh
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Publication number: 20090024684Abstract: A method for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.Type: ApplicationFiled: September 26, 2008Publication date: January 22, 2009Applicant: IBM CORPORATIONInventors: Sang Hoo Dhong, Harm Peter Hofstee, Christian Jacobi, Silvia Melitta Mueller, Hwa-Joon Oh
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Patent number: 7469265Abstract: In a first aspect, a method is provided for determining in which of n intervals a sum of two or more numbers resides. The method includes determining the two or more numbers, and providing fewer than n compress circuits each adapted to (1) input the two or more numbers; (2) input range information regarding ranges used to define the n intervals; and (3) compress the two or more numbers and the range information into two or more outputs. The method further includes employing the fewer than n compress circuits to determine in which of the n intervals the sum of the two or more numbers resides. Numerous other aspects are provided.Type: GrantFiled: October 16, 2003Date of Patent: December 23, 2008Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Silvia Melitta Mueller, Hiroo Nishikawa, Hwa-Joon Oh
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Patent number: 7447725Abstract: An apparatus for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.Type: GrantFiled: November 5, 2004Date of Patent: November 4, 2008Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Harm Peter Hofstee, Christian Jacobi, Silvia Melitta Mueller, Hwa-Joon Oh
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Publication number: 20080263336Abstract: High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, significantly less overhead is incurred than would be incurred with specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic.Type: ApplicationFiled: June 24, 2008Publication date: October 23, 2008Applicant: International Business Machines CorporationInventors: Sang Hoo Dhong, Gordon Clyde Fossum, Harm Peter Hofstee, Brad William Michael, Silvia Melitta Mueller, Hwa-Joon Oh
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Publication number: 20080195684Abstract: The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is configured to compute a value in a plurality of shift stages, and wherein a bit group of the shift amount is employable to affect at least one of the plurality of shift stages, thereby decreasing processing time.Type: ApplicationFiled: April 18, 2008Publication date: August 14, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sang Hoo Dhong, Christian Jacobi, Silvia Melitta Mueller, Hiroo Nishikawa, Hwa-Joon Oh
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Patent number: 7406589Abstract: High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, significantly less overhead is incurred than would be incurred with specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic.Type: GrantFiled: May 12, 2005Date of Patent: July 29, 2008Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Gordon Clyde Fossum, Harm Peter Hofstee, Brad William Michael, Silvia Melitta Mueller, Hwa-Joon Oh
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Patent number: 7392270Abstract: The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is configured to compute a value in a plurality of shift stages, and wherein a bit group of the shift amount is employable to affect at least one of the plurality of shift stages, thereby decreasing processing time.Type: GrantFiled: July 29, 2004Date of Patent: June 24, 2008Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Christian Jacobi, Silvia Melitta Mueller, Hiroo Nishikawa, Hwa-Joon Oh
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Patent number: 7290023Abstract: A floating point unit (FPU) which generates a correction signal and an inverted leading zero signal. Exponent logic, is configured to generate an exponent value, a first incremented exponent value, and a second incremented exponent value. Exponent adjust and rounding logic configured to receive the exponent value, the first incremented exponent value, and the second incremented exponent value. The exponent adjust and rounding logic is further configured to add the inverted leading zero signal to the first incremented exponent value and the second incremented exponent value, thereby producing an exponent output value, a first incremented exponent output value, and a second incremented exponent output value. Either the exponent output value, the first incremented exponent output value, or the second exponent output value are then selected.Type: GrantFiled: November 20, 2003Date of Patent: October 30, 2007Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Silvia Melitta Mueller, Hwa-Joon Oh, Kevin D. Tran
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Patent number: 7245159Abstract: A method, a computer program, and an apparatus are provided to protect transmission gates in a multiplexer (mux). Because transmission gates are much faster than the more convention AND-OR arrays, transmission gate usage in muxes are being used more often in high speed circuitry. However, transmission gate have a significant problem in that short circuit are possible for situations where there is not a one-hot select signal. Therefore, to eliminate the problem, logic gates are utilized specifically during Power-On Reset (POR) to force a one-hot selection to prevent any possible short circuits.Type: GrantFiled: July 15, 2004Date of Patent: July 17, 2007Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Christian Jacobi, Hwa-Joon Oh, Silvia Melitta Mueller
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Patent number: 7237163Abstract: An apparatus, a method and a computer program are provided to reduce leakage current in a processor. Traditionally, extra logic is employed to reduce leakage currents. However, reducing leakage current without sacrificing fine grain operations and speed can be difficult. Achieving such a goal can be accomplished by incorporating a multiplexer (mux) into the scan-in path of scan registers so that units or sub-units of the processor can be powered down individually. Additionally, the muxes are not incorporated into time paths, so speed can be preserved.Type: GrantFiled: November 5, 2004Date of Patent: June 26, 2007Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Hwa-Joon Oh, Silvia Melitta Mueller, Joel Silberman
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Publication number: 20070061553Abstract: A disclosed byte execution unit receives byte instruction information and two operands, and performs an operation specified by the byte instruction information upon one or both of the operands, thereby producing a result. The byte instruction specifies either a count ones in bytes operation, an average bytes operation, an absolute differences of bytes operation, or a sum bytes into halfwords operation. In one embodiment, the byte execution unit includes multiple byte units. Each byte unit includes multiple population counters, two compressor units, adder input multiplexer logic, adder logic, and result multiplexer logic. A data processing system is described including a processor coupled to a memory system. The processor includes the byte execution unit. The memory system includes a byte instruction, wherein the byte instruction specifies either the count ones in bytes operation, the average bytes operation, the absolute differences of bytes operation, or the sum bytes into halfwords operation.Type: ApplicationFiled: November 1, 2006Publication date: March 15, 2007Inventors: Sang Dhong, Hwa-Joon Oh, Brad Michael, Silvia Mueller, Kevin Tran
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Patent number: 7149877Abstract: A disclosed byte execution unit receives byte instruction information and two operands, and performs an operation specified by the byte instruction information upon one or both of the operands, thereby producing a result. The byte instruction specifies either a count ones in bytes operation, an average bytes operation, an absolute differences of bytes operation, or a sum bytes into halfwords operation. In one embodiment, the byte execution unit includes multiple byte units. Each byte unit includes multiple population counters, two compressor units, adder input multiplexer logic, adder logic, and result multiplexer logic. A data processing system is described including a processor coupled to a memory system. The processor includes the byte execution unit. The memory system includes a byte instruction, wherein the byte instruction specifies either the count ones in bytes operation, the average bytes operation, the absolute differences of bytes operation, or the sum bytes into halfwords operation.Type: GrantFiled: July 17, 2003Date of Patent: December 12, 2006Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Hwa-Joon Oh, Brad William Michael, Silvia Melitta Mueller, Kevin D. Tran
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Publication number: 20060259745Abstract: A preferred embodiment of the present invention provides a method, computer program product, and processor design for supporting high-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, a preferred embodiment of the present invention incurs significantly less overhead than would specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic.Type: ApplicationFiled: May 12, 2005Publication date: November 16, 2006Inventors: Sang Dhong, Gordon Fossum, Harm Hofstee, Brad Michael, Silvia Mueller, Hwa-Joon Oh
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Patent number: 7137021Abstract: A method and an apparatus are provided for saving power in a microprocessor. The microprocessor has at least one functional unit, which has a plurality of blocks. The blocks each include a plurality of sub-blocks. It is determined whether there is any instruction for the functional unit. Upon a determination that there is no instruction for the functional unit, the functional unit is shut down. Upon a determination that there is at least one instruction for the functional unit, at least one inactive block of the functional unit is shut down based on the instruction.Type: GrantFiled: May 15, 2003Date of Patent: November 14, 2006Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Silvia Melitta Mueller, Hwa-Joon Oh
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Patent number: 7058830Abstract: The present invention provides for saving power in a floating point unit. Bypass logic is coupled to the input of the aligner and the multiplier. An aligner bypass is coupled to the output of the aligner and an output of the bypass logic. A multiplier bypass is coupled to the output of the multiplier and an output of the bypass logic. The aligner bypass and the multiplier bypass transmit the output of the aligner and multiplier, or the bypass logic, as a function of an aligner bypass signal and a multiplier bypass signal, respectively. An adder is coupled to the output of the aligner bypass and the multiplier bypass. Clock disable logic is used to selectively enable and disable at least portions of the aligner, multiplier and bypass logic. This is done based on the operation and on the value of the operands.Type: GrantFiled: March 19, 2003Date of Patent: June 6, 2006Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Silvia Melitta Mueller, Hwa-Joon Oh, Kevin Duc Tran