Abstract: A display device is provided including a substrate. A second semiconductor layer is disposed on the substrate. The second semiconductor layer includes Si. A second gate lower electrode overlaps a channel region of the second semiconductor layer. A second gate insulating layer is disposed on the second gate lower electrode. A second gate upper electrode and a light blocking layer are disposed on the second gate insulating layer. A first auxiliary layer is disposed on the second gate upper electrode and the light blocking layer. A first semiconductor layer overlaps the light blocking layer. The first semiconductor layer includes an oxide semiconductor. A first gate electrode overlaps a channel region of the first semiconductor layer. The first auxiliary layer includes an insulating layer including at least one compound selected from SiNx, SiOx, and SiON, and at least one material selected from F, Cl, and C.

Abstract: A capacitor component includes a body, including a dielectric layer and an internal electrode layer, and an external electrode disposed on the body and connected to the internal electrode layer. At least one hole is formed in the internal electrode layer, and a region, containing at least one selected from the group consisting of indium (In) and tin (Sn), is disposed in the hole. A method of manufacturing a capacitor component includes forming a dielectric green sheet, forming a conductive thin film, including a first conductive material and a second conductive material, on the dielectric green sheet, and sintering the conductive thin film to form an internal electrode layer. The internal electrode layer includes the first conductive material, and a region, including the second conductive material, is formed in the internal electrode layer.

Abstract: A secondary battery having improved impact resistance is provided. The secondary battery includes a battery case comprising an electrode assembly and an electrolyte accommodated in an accommodation part of the battery case. The secondary battery satisfies following Equation (1): Equation (1): W/S?42. In Equation (1), W is an amount of electrolyte per unit capacity of the secondary battery [unit: g/Ah], and S is a product of a total length [unit: m] and a full width [unit: m] of the electrode assembly.

Abstract: Disclosed is a blankmask for EUV lithography, including a reflective film, a capping film and a phase shift film which are sequentially formed on a substrate. The phase shift film includes a first layer containing niobium (Nb) and chrome (Cr), and a second layer containing tantalum (Ta) and silicon (Si). In the first layer, the content of niobium (Nb) ranges from 20 to 50 at %, and the content of chrome (Cr) content ranges from 10 to 40 at %. The blankmask can implement an excellent resolution and NILS, and implement a low DtC.

Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.

Abstract: A multilayer capacitor includes a capacitor body including dielectric layers and internal electrodes alternately disposed with the dielectric layers interposed therebetween; and an external electrode disposed on the capacitor body to be connected to one or more of the internal electrodes. Porosity of ends of the internal electrodes is less than 50% on an interfacial surface between a margin of the capacitor body in a width direction the capacitor body and the internal electrodes.

Abstract: One aspect of the present disclosure is a pharmaceutical composition which includes (R)—N-[1-(3,5-difluoro-4-methansulfonylamino-phenyl)-ethyl]-3-(2-propyl-6-trifluoromethyl-pyridin-3-yl)-acrylamide as a first component and a cellulosic polymer as a second component, wherein the composition of one aspect of the present disclosure has a formulation characteristic in which crystal formation is delayed for a long time.

Abstract: A method in which a high-quality packet telephony terminal apparatus performing low-latency and lossless packet communication with a counterpart packet telephony terminal apparatus operates in an integrated network structure in which a time sensitive network (TSN) and a packet communication network are combined may be disclosed. The packet telephony terminal apparatus may perform packet telephony call processing, perform a TSN stream reservation procedure when the counterpart packet telephony terminal apparatus is capable of performing a TSN function for lossless packet communication, adjust a size of a dejitter buffer when the TSN stream reservation procedure is successful, and perform low-latency packet telephony communication through the minimized size of the dejitter buffer.

Abstract: An apparatus for fabricating a display panel, including a film fixing module configured to fix a stretched film on which a plurality of light emitting elements are arranged, a film pressurizing module configured to pressurize the stretched film, a first thickness detection module configured to detect, at each pressurization step, a modulus of elasticity and a change in thickness of the stretched film that is pressurized and stretched by the film pressurizing module, a second thickness detection module configured to detect, at each pressurization step, a change in thickness of an adhesive applied in a front direction of the stretched film, an image detection module configured to photograph the plurality of light emitting elements arranged on the stretched film for each pressurization step and to detect a change in arrangement information of the light emitting elements, and a main processor configured to database feature change information.

Abstract: An apparatus for fabricating a display panel, the apparatus including: a loading module configured to accommodate a large-area fabricating substrate, the loading module being configured to adjust an inclination of the large-area fabricating substrate from a rear surface of the large-area fabricating substrate and to press the large-area fabricating substrate; and an element transfer module configured to transfer a plurality of light emitting elements or an integrated circuit onto the large-area fabricating substrate and configured to bond and press a wafer on which the plurality of light emitting elements or the at least one integrated circuit is located onto the large-area fabricating substrate.

Abstract: The present disclosure relates to a toxic waste treatment process and treatment apparatus including: a temperature raising operation of raising a temperature of a toxic waste solid to a heat treatment temperature selected from 300° C. to 600° C. at an average temperature raising rate of 5° C./min or less; and a heat treatment operation of heat-treating the toxic waste solid at the heat treatment temperature.

Abstract: A substrate processing method is provided. The substrate processing method comprises loading a substrate onto a substrate support inside a chamber, forming a plasma inside the chamber, providing a first DC pulse signal to an electromagnet that generates a magnetic field inside the chamber and processing the substrate with the plasma, wherein the first DC pulse signal is repeated at a first period including a first section and a second section subsequent to the first section, the first DC pulse signal has a first level during the first section, and the first DC pulse signal has a second level different from the first level during the second section.

Abstract: A thin film transistor includes a substrate; an active layer including a channel area, a first conductive area, and a second conductive area; a gate insulating layer on a portion of the active layer; a first through hole penetrating through a portion of the first conductive area; a second through hole penetrating through a portion of the second conductive area; a gate electrode overlapping the channel area of the active layer; a first electrode electrically connected to the first conductive area; and a second electrode electrically connected to the second conductive area. One side of the first electrode adjacent to the first through hole is parallel to the one side of the first through hole, the first electrode including protrusion parts at both ends thereof and a groove part concavely recessed from the gate electrode.

Abstract: A display device including a window, a display panel, and an input detection sensor disposed therebetween and including a first electrode extending in a first direction, a second electrode extending in the first direction, a third electrode intersecting with the first and second electrodes while insulated therefrom, a first signal line electrically connected to an end of the first electrode, a second signal line electrically connected to an end of the second electrode, and a third signal line and a fourth signal line electrically connected to a first end and a second end of the third electrode, respectively, in which each of the first and second signal lines includes a first part and a second part extending in the first direction and disposed between the first part of the first signal line and the second part of the first signal line in a second direction crossing the first direction.

Abstract: A memory allocation device includes a storage including at least one memory pool in which a memory piece used to search for a route is previously generated and a controller that determines whether it is possible to search for the route using the previously generated memory piece and determines an added amount of memory pieces to previously allocate a memory of the storage, when it is impossible to search for the route.

Abstract: An electronic device includes a target address generation circuit configured to generate a counting signal by counting the number of times each logic level combination of an address is input by performing an internal read operation and an internal write operation during an active operation, configured to store the counting signal as the storage counting signal when the counting signal is counted more than a storage counting signal that is stored therein, and configured to store the address, corresponding to the counting signal, as a target address; and a refresh control circuit configured to control a smart refresh operation on the target address.

Abstract: A semiconductor memory device includes a substrate; a bit-line on the substrate and extending in a first direction; first and second channel patterns on the bit-line; the second channel pattern being spaced apart from the first channel pattern in the first direction; a first word-line between the first and second channel patterns and extending in a second direction that intersects the first direction; a second word-line between the first and second channel patterns, extending in the second direction, and being spaced apart from the first word-line in the first direction; capacitors on and connected to the channel patterns; wherein the first and second channel patterns include first and second metal oxide patterns sequentially on the bit-line, each of the first and second metal oxide patterns include an amorphous metal oxide, and a composition of the first metal oxide pattern is different from a composition of the second metal oxide pattern.

Abstract: A polymer electrolyte membrane having improved chemical or mechanical durability is provided. The present disclosure relates to a polymer electrolyte membrane, and the polymer electrolyte membrane according to the present disclosure comprises a porous support and a composite layer containing a first ionomer filled in the porous support, wherein the polymer electrolyte membrane comprises a first segment having a first durability and a second segment having a second durability, and the first durability is higher than the second durability.

Abstract: A display device includes a thin-film transistor, a source/drain electrode and an auxiliary electrode including a first conductive layer and a second conductive layer disposed on the first conductive layer, a via insulating layer having a first opening exposing the auxiliary electrode, a capping layer covering a portion of the auxiliary electrode and a light emitting material layer and a common electrode layer sequentially stacked on the via insulating layer and the capping layer, wherein the source/drain electrode is electrically connected to the thin-film transistor through a contact hole penetrating the interlayer insulating layer, the auxiliary electrode has an undercut, and the capping layer includes a first capping layer covering side surfaces of the first conductive layer of the auxiliary electrode and a second capping layer separated from the first capping layer and disposed on the second conductive layer of the auxiliary electrode.

Abstract: A multilayer ceramic capacitor includes: a ceramic body including dielectric layers and first and second internal electrodes disposed to face each other with respective dielectric layers interposed therebetween; and first and second external electrodes disposed on an external surface of the ceramic body, wherein the dielectric layer contains a barium titanate-based powder particle having a core-shell structure including a core and a shell around the core, the shell having a structure in which titanium is partially substituted with an element having the same oxidation number as that of the titanium in the barium titanate-based powder particle and having an ionic radius different from that of the titanium in the barium titanate-based powder particle, and the shell covers at least 30% of a surface of the core.